SU951398A1 - Programmable read-only memory with checkup capability - Google Patents

Description

(B) PROGRAMMABLE PERMANENT STORAGE DEVICE WITH CONTROL

one

The invention relates to computing and can be used in the creation of large integrated circuits - storage devices.

Semiconductor memory devices are known, which have different volumes and functional circuits of memory matrices p.

The closest to the invention to the technical essence is a JQ miner, containing a row decoder, a memory matrix, a synchronization and control device, an input / output device, a column decoder, and a buffer register, whether the G2 column is amplified,

The disadvantages of this device are the complexity and the long monitoring time due to the large volume of test equipment during production, testing and input control of products. In addition, test equipment is much more complex when conducting dynamic tests and controlling operation at extreme frequencies because of the need to introduce complex test and test circuits, signal conditioners, comparators, dynamic switches and other matching devices into the control system. approach the pins of a controlled integrated circuit to eliminate the effects of mechanical contacting devices and long connections between the pins of the tral circuit and the terminal system during dynamic tests on the functioning and control of limit frequencies.

The purpose of the invention is to increase the reliability of the device by eliminating the influence of mechanical contacting devices and long connections between the pins of the integrated circuit and the pins of the system during dynamic monitoring and control of functioning at limiting frequencies, which leads to

simplification of instrumental means of automatic control during production, testing and input control of products.

The goal is achieved by the fact that F3 is a programmable read-only memory with a control containing a buffer register, the outputs of which are connected via the decoder to the outputs of the amplifier unit, the outputs 0 of which are connected to the corresponding inputs and outputs of the matrix on the opitel, the synchronization unit whose outputs are connected to clock inputs of the buffer register, an amplifier unit and an I / O unit, the informational input-output of which is connected to the input-output of the decoder, the first input is with the input bus, the output is with the output th data line, generator, whose output is connected to the input of the driving-pulse and the first audio-input register counter, which outputs are connected to the first address input of the commutator 25, the control block. The outputs whose outputs are connected to the inputs of the buffer register are entered into a comparison unit and two OR blocks, the first inputs of which are connected to the first and second outputs of the control pulse generator, the second inputs of the OR blocks are the enable and write-read inputs of the device, and the outputs of the blocks OR are connected respectively to the second input of the synchronization unit and the second input of the input / output unit; the first input of the comparison unit is the control input of the device; the second input of the comparison unit is connected to the third input of the unit a control pulse cell, the third input of the comparison unit is a mode setting input and is connected to the second counter-register input and the control input of the switching unit, the fourth input of the comparison unit is connected to the output of the I / O unit, and the output is connected to the pulse generator input and is the output of the monitoring result of the device, and the input of the pulse generator is the synchronization output of the device. The above listed blocks and communications, made by the same technology and on a single chip with a known one, ensure autonomous operation of the device when signals are applied to the device Mode selection, Control, Record-read, in mode of smith, and Select mode, Information and Record-read in mode records, while there are no strict requirements for the fronts of these signals, so the mechanical contacting device and long connections do not have parasitic effects. The remaining signals (addresses, service) are as close as possible and are fully consistent with the inputs of the functional blocks of the device.

Claims (2)

In addition, in the manufacture of integrated circuits, there is no need for sophisticated automated control systems such as Vizir, Elekon-FZU during climatic tests, tests for reliability and durability, and input control, significantly (non-standard hardware means are simplified to ensure the functioning and control of products. The drawing shows a block diagram of the proposed programmable read-only memory with the device made in the form of an integrated circuit and functionally consists of a generator a and | pulses 1, counter-register 2, switching unit 3, control pulse generator k, first 5 and second 6 OR blocks, buffer register 7, decoder 8, amplifier unit 9, matrix accumulator 10, synchronization unit 11, input unit - output 12, comparator unit 13. The device also contains control outputs. The device operates as follows in the monitoring mode. In read mode, a signal is received at input 18, and a signal is output at the AND output, which selects the internal address bus of the switching unit 3, resetting sets the register-register 2 to the initial state and sets the output trigger of the comparison block 13 to the state that starts the pulse generator 1. The pulses from the generator 1 arrive at the input of the counter-register 2, the outputs of which are used as internal address buses entering the block switching 3 and further to the address inputs of the register 7- At the same time from the controlled pulse generator 1 /, the output 1b receives pulses that can be used as a clock signal for external control devices. In addition, the pulses are fed to the input of the imager and control pulses k. Shaper k outputs pulses Resolution, Write-read and strobe information analysis. Pulses Resolution and Write-read are received through blocks OR 5 and 6 to the blocks of synchronization 11 and input-output 12, respectively. An information analysis gate arrives at a comparison unit 13, where a comparison of the information generated by the matrix storage 10 and the control, which comes from an external device to the output 23, occurs. In the case of uneven information, the analysis circuit outputs a control result to the external output 2 and pulse generator input which stops. When monitoring permanent storage devices, programmable storage devices in a memory matrix, as a rule, they are the same (| memory in all cells is the same: either logical O or logical 1, depending on the manufacturing technology, and the control signal is simply a constant level of either a logical 0 or a logical one. When monitoring storage devices with recorded information, the control signal can be generated by an external device that is synchronized by a pulse of sync from the external output 16. In the recording mode, the corresponding signal from the external device is fed to output 18. Then, the mode selection signal is sent to the external output k, then the pulse generator 1 is turned on and outputs a synchronization pulse to the external output 16, starts the counter-register 2 and the control pulse generator Z, which generates pulses Resolution and Read-write to synchronization and input-output units through blocks OR 5 and 6. Input input of output unit 12 from external device through output 20 is fed with input information synchronously with the operation of the account tchik-register 2. In the operating mode, the device operates similarly to the prototype, except that the inhibit signal is output to the T terminal. The use of the proposed device significantly reduces the cost of the control process during production, testing and input control by simplifying the instrumental means of control, and also significantly reduces the cost of operating the equipment and developing software and mathematics. Invention Programmable read-only memory with control containing buffer register, outputs of which are connected via decoder to inputs of amplifier unit, outputs of which are connected with corresponding inputs and outputs of matrix accumulator, synchronization unit, outputs of which are connected to clock inputs of buffer register, amplifier unit and an input / output unit, information input-output, which is connected to the input-output of the decoder. the first input is with the input bus, and the output is with the output information bus, a generator, the output of which is connected to the input of the control pulse shaper and the first input of the counter-register whose outputs are connected to the first address inputs of the switching unit whose outputs are connected to the inputs of the buffer register, that, in order to increase the reliability of the device, a comparison block and two OR blocks are entered into it, the first inputs of which are connected to the first and second outputs of the control pulse former, the second inputs of the block OR s are the device's resolution and write-read inputs, respectively, and the OR block outputs are connected to the second input of the synchronization unit and the second input of the I / O ferip, the first ECU of the comparison unit is the control input of the device, and the second input of the comparison unit is connected to the third input. control pulse generator, the third input of the comparison unit is the mode setting input and is connected to the second input of the counter-register and to the control input of the switching unit, the fourth input of the comparison unit yield N input-output unit, and an output coupled to the pulse generator input and the output is a control device The results, and the input n