RU1833919C - Device for ram unit check - Google Patents

Abstract

The invention relates to computer technology and can be used for functional control of RAM of large information capacity. The purpose of the invention is to increase the reliability of monitoring by more fully detecting faults from the mutual influence of memory cells. The device comprises an address counter I, a write-read trigger 2, a display unit 3, a frame counter 4, a comparison unit 5, a first trigger 7, a generator 7, a sampler 8, a second trigger 9, a one-shot 10, a first demultiplexer I1, a second demultiplexer 12 , the first element OR 13, the second element OR 14, the first multiplexer 15 and the second multiplexer 16, the delay element 17. 1 il.

Description

The invention relates to computer technology and can be used for functional control of semiconductor RAM chips.

The aim of the invention is to increase the reliability of control by more fully detecting faults in the mutual influence of memory.

The drawing shows a diagram of a device for monitoring RAM.

The device comprises an address counter 1, a write-read trigger 2, a display unit 3, a frame counter 4, a comparison unit 5, a first trigger 6, a generator 7, a sampler 8, a second trigger 9, a single vibrator 10, a first demultiplexer 11, a second demultiplexer 12, first OR element 13, second OR element 14, first multiplexer 15 and second multiplexer 16, delay element 17.

The device has the following communication structure. The first input of the display unit 3 is the information input of the device, the first control output of which is the input of the sampler 8, the input of which and the first input of the comparison unit 5 are combined and connected to the output of the generator 7. The direct output of the write-read trigger 2 is the second control output of the device, the information output of which is the output of the comparison unit 5, the inputs of the first group of which are connected to the information outputs of the address counter 1 and are the address outputs of the device. The information outputs of the frame counter 4 are connected to the inputs of the second group of the comparison unit 5. The second input of which and the second input of the display unit 3 are combined and connected to the direct output of the first trigger 5. The input of the second trigger 9 is connected

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whose to the inverse output of the first trigger 6, the input of which is connected to the output of the second multiplexer 16, the first and second BXOVs of which are connected respectively to the outputs of the forward and reverse transfer of frame counter 4, the inputs of the forward and reverse counts of which are connected to the first and second the outputs of the second demultiplexer 12, the input of which is connected to the output of the second element OR 14, the first input of which is connected to the inverse output of the write-read trigger 2, the output of which is connected to the output of the first multiplexer 15. The first and second input the first multiplexer 15 are connected respectively to the outputs of the forward and reverse transfer of the counter of address 1, the inputs of the forward and reverse counts of which are connected respectively to the first and second outputs of the first demultiplexer 11, the input of which is connected to the output of the first element OR 13, The first input of the element OR 13 is connected with the output of the generator 7, the input of which, the input of the one-shot 10, the control inputs of the first 11 and second 12 demultiplexers and the input of the delay element 17 are combined and connected to the direct output of the second trigger 9, inverse th output is connected to the third input of the display unit 3, second inputs of first 13 and second 14 OR elements are coupled and connected to the output of the monostable 1-0. The control inputs of the first 15 and second 16 multiplexers are combined and connected to the output of the delay element 17.

The device / operates as follows. Comparison unit 5 performs a bitwise comparison of the status of the address counter 1 and the frame counter 4. The result of the comparison is written to the checked memory at the address determined by the counter 1 of the address. The pulse from the generator 7 by the leading edge gates the block 5, the unit goes to the counter 1 of the address at its trailing edge, as a result of which the state of the counter 1 of the address and the counter 4 frames is compared, and then a new address appears. At the beginning of operation, the counters 1,4 and the triggers 2,6,9 are reset to zero. As a result of comparing the states of the counters 1 and 4, the comparison unit 5 produces a logical unit, which is written to the test memory at the zero address. Subsequently, as pulses from the generator 7 arrive, which pass through the first OR element 13 and the first demultiplexer 11 to the input of the direct counter of address counter 1, there is a constant non-comparison of the states of counters 1 and 4 and to all addresses of the memory being checked This records zeros.

The overflow pulse from the direct transfer output of address counter 1 passes through the first multiplexer 15 and sets the write-read trigger 2 to the logical unit state, which sets the read mode from the memory being checked. Next, information is read at all addresses, at the end of which, as a result of reverse tipping of the write-read trigger 2, the signal from its inverse output, passes through the second element OR 14 and the second demultiplexer 12, will go to the input of the direct account and write the unit to the frame counter 4. In the next frame of the recording, the unit will be recorded at the first address, since the comparison unit 5 will work when the states of counters 1 and 4 coincide. Zero information will be recorded on all other memory cells.

Such a sequence of work will be observed until the end of the first cycle, i.e., when the pulse from the output of the direct transfer of frame counter 4, passing through the second multiplexer 16, does not set the first trigger 6 to the state of a logical unit. In the second cycle, the control unit is under the influence of a signal from the direct output of the first trigger 6. 5 will provide inverse information with respect to that generated in the first cycle. At the same time, the same signal sets the display unit 3 to invert information received at the information input of the device. Thus, by the end of the second cycle, exactly 2 units should be written to the display unit 3, in case of correct operation of the memory being checked. At the end of the second control cycle, the pulse from the output of the direct transfer of the frame counter 4, passing through the second multiplexer 16, will overturn the first trigger 6 to the state

logical zero. The positive edge of the pulse from the inverse output of trigger 6 will write a logical unit to the second trigger 9. This value from the direct output of the second trigger 9 will go to the control inputs of the first and second demultiplexers 11 and 12, which will switch to the mode of connecting the counting pulses to the inputs of the counting counters 1 and 4. After completion of the switching processes, the decay of the short signal from the output of the one-shot 10 , which was started by a differential at the direct output of trigger 9, the unit is subtracted from counters 1 and 4. Since after the end of the second control cycle these counters were in the zero state, then after subtracting the unit they will go into cost all units.

After that, the first and second multiplexers 15 and 16, under the action of a control signal supplied to them from the direct output of the second trigger 9 through the delay element 5, 17, the reverse transfer outputs of the counters 1 and 4 are switched to the inputs of the triggers 2 and 6, respectively.

Further operation of the device during the third and fourth cycles / which will begin at the moment of the next pulse from the generator 7 will differ from the operation during the first and second cycles only by enumerating the addresses of memory cells - 15 in order of decreasing. At the end of the fourth cycle, the second trigger 9 will return to the zero state, which will stop the generator 7 and issue commands to the display unit 3 for indication. If exactly 20 units are written into the display unit 3 during 20 m of four control cycles, this will lead to the display of the Good date, in all other cases, a malfunction of the tested RAM will be recorded.

Claims (1)

Formula from Acquisition A RAM monitor device comprising a display unit, a re-30 speaker, a sampler, a write-read trigger, an address counter, a frame counter, a comparison unit, a first trigger, the first input of the display unit being the information input 35 device, the first control input of which is the output of the signal generator of the sample, the input of which and the first 40 input of the comparison unit are combined and connected to the output of the generator, the direct output of the write-read trigger is the second control yuschim output device, the information output of which is - 45 comparing an output unit, the inputs of the first group are connected to data outputs of the address counter and outputs are addressable device data outputs of the counter 50 frames are connected to the inputs of the second group of the comparison unit, the second input of which and the second input of the display unit are combined and connected to the direct output of the first trigger, characterized in that, in order to increase the reliability of the control by detecting faults from the mutual influence of memory, a second trigger, a one-shot, a delay element, the first and second multiplexers, the first and second multiplexers, the first and second elements OR, the input of the second trigger is connected to the central output of the first trigger, the input of which is connected to the output of the second multiplexer, the first and second inputs of which are connected respectively to the outputs of the forward and reverse transfer of the frame counter, the inputs of the forward and reverse counts of which are connected to the first and second outputs of the second demultiplexer, the input of which is connected to the output of the second OR element, the first input of which is connected to the inverse output of a write-read trigger, the input of which is connected to the output of the first multiplexer, the first and second inputs of which are connected respectively to the outputs directly first and second counts of the address, the inputs of the forward and reverse counts of which are connected respectively to the first and second outputs of the first demultiplexer, the input of which is connected to the output of the first OR element, the first input of which is connected to the output of the generator, the input of which, the input of the one-shot, controls the input inputs of the first and second demultiplexers and the input of the delay element are combined and connected to the direct output of the second trigger, the inverse output of which is connected to the third input of the display unit, the second inputs of the first and W cerned OR elements are coupled and connected to the output of the monostable, control inputs of the first and second multiplexers are combined and connected to the output of the delay element.