SU1536444A1 - Device for checking multidigital memory units - Google Patents

Abstract

The invention relates to computing and can be used to control multi-bit memory blocks, as well as for functional control of RAM chips. The purpose of the invention is to increase the reliability of the control. The device contains a clock signal generator 1, a start-stop unit 2, a first trigger 3, a first counter 4, a second trigger 5, a second counter 6, a chip select signal forming unit 7, a persistent memory block 8, comparison units 9, blocks display 10, a multi-bit memory unit 11. 2 Il.

Description

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The invention relates to computing and can be used to control multi-bit memory blocks, as well as for functional control of RAM chips.

The purpose of the invention is to increase the reliability of the control.

FIG. 1 shows a diagram of a device for monitoring multi-bit memory blocks; in fig. 2 is an example of a possible practical implementation of the proposed device.

The device (Fig. 1) contains a clock signal generator 1, a start-stop unit 2, a first trigger 3, a first counter 4, a second trigger 5, a second counter 6, a signal generation block 7, a chip selector, a permanent memory unit 8, 11 comparison units 9, group M of display units 10, multi-digit memory unit 11. FIG. 1 is indicated: n is the number of address inputs of the monitored multi-bit memory unit 11; M is the number of information inputs of the controlled multi-bit memory block 11; K - the size of the additional counter 6.

The device works as follows.

The monitoring of multi-bit memory blocks is carried out in two stages.

At the first stage of control, malfunction of the chip selection circuit is revealed. Using the signal generator 7, Selection of a cryp-off circuit, the Selection of the crystal is switched off. On a Start command from the start-stop unit 2, the device generates control signals and a write test sequence. With the circuits turned off, the choice of a crystal controlled multi-bit memory block I1 should not write and read test information.

Presence of a signal A marriage at the first stage of monitoring indicates that the monitored multi-bit memory unit 11 has uncorrectable defects in the circuit. The choice of the chip is not subject to further control.

At the second stage of monitoring, the device also operates in two modes: in the mode of recording information by addresses and in the mode of reading the recorded information, in which the malfunctions of the tested multi-bit memory unit are detected.

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Before the operation of the device, the first trigger 3, the first counter 4, the second trigger 5, the second counter 6 are in the zero state. Before the beginning of the second stage of control using the chip selector chip, the chip select circuit is turned on, then, at the start command, the start-stop unit 2 starts the clock signal generator 1, which begins to emit clock pulses to the first inputs M of the display units 9 and to the counting input of the first counter 3 .

The second trigger 5 generates a code that provides the implementation of the write and read modes: O - write, 1 - read information for the controlled multi-bit memory block.

The address code enters the multi-bit memory block from the outputs of counter 4, and the same code goes to the n inputs of the lower addresses of the bits of the 8 permanent memory. To the upper address bits of the memory block, a code is supplied from the corresponding outputs of the second counter 6,

The permanent memory unit 8 generates a test sequence that arrives at both the information inputs of the monitored multi-bit memory unit 11 and the second inputs M of the comparison units 9, the first inputs of which are supplied with a test sequence readable from the monitored multi-digit memory unit. And comparison blocks 9 serve to compare the data read from the monitored multi-bit memory block 11 at specified address sequences with data recorded at the same address sequence, and operate as follows.

The codes read from the monitored multi-bit memory unit 11 are unchanged on the first inputs M of the comparison units 9, which perform bitwise comparison of the incoming codes. According to the results of the comparison of information recorded in the monitored multi-bit memory block 11 read out of it, the marriage signals are generated, which from the output M of the comparison units 9 arrive at the second inputs M of the display units 10 where the fault is fixed.

In this case, the Marriage signal is formed and the display element lights up, according to which the fault is fixed in the corresponding bit of the monitored multi-bit memory unit 11.

At the end of the monitoring cycle (after all the test sequences previously recorded in block 8 of the permanent memory are read from it) with full coincidence of the information recorded in the monitored multi-bit memory block 11 with information j read from this memory block, the second counter 6 generates a signal that enters the block 2 start-stop, which in turn generates a Stop signal, according to which the generator 1 of clock signals stops the formation of clock pulses.

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Claims (1)

Claims An apparatus for monitoring multi-bit memory blocks comprising a clock signal generator, a first counter, a first clock signal generator input is an input for setting a device mode, characterized in that, in order to increase the control reliability, the first and second triggers are entered into the device, the second counter, the signal-shaping unit, the chip selection, the fixed memory block, the group of comparison blocks, the inverse output of the first flip-flop is connected to the sync input five 0 five 0 five the first counter, the transfer output of which is connected to the synchronization input of the second trigger, the inverse output of which is connected to the synchronization input of the second counter, the first output of the clock signal generator output is the device sync output, the second output of the clock signal generator is connected to the synchronization input of the first trigger, pr My output is connected to the input of the signal conditioning unit. Choosing a chip, the output of which is the output of the device sampling resolution, the inputs of the initial setup first and second counters are combined and are the corresponding input of the device, the transfer output of the second counter is the output. The end of the device operation, the outputs of the group of comparison blocks are outputs of the control result of the device, the direct output of the second trigger is the write-read output the devices, the outputs of the first counter are connected to the inputs of the first group of the permanent memory unit and are the device’s output outputs, the inputs of the second group of the permanent memory unit are connected to the outputs of the second th counter unit outputs a constant memory coupled to the inputs of the second group and the comparison block information are output devices, input unit comparing the first group are information inputs.