SU1249588A1 - Device for checking integrated circuits of internal memory - Google Patents

Abstract

The invention relates to automation and computing and can be used for the functional control of large integrated memory circuits. The circuit of the invention is to simplify the device. The device contains an address counter, a write-read trigger, a control unit, a frame counter, a comparison unit, a stop trigger, a generator, and a sampling signal generator. The outputs of the address counter and the frame counter are connected to the JV inputs of the comparison unit, the output of which is the information output of the device. The device checks that the readings of the unit (zero) are correct against the background of all zeros (ones) for each cell of the checked integrated memory chip. 1 il. ABOUT)

Description

The invention relates to automation and computing and can be used for the functional control of large integrated memory circuits.

The purpose of the invention is to simplify the device.

The drawing shows a diagram of a device for monitoring integrated memory microcircuits.

The device contains a counter 1 address trigger 2 write-read block

3control, 4 frames counter, block

5 comparisons, stop trigger 6, generator 7 and sampling signal generator 8.

The control unit 3 contains a one-oscillator 9, a display unit 10, a controlled inverter 11, a result counter 12, an AND element 13 and an indication trigger 14. Also shown is the connection of the tested microcircuit 15 to the device.

The device for controlling integrated memory microcircuits operates as follows.

Comparison unit 5 performs a one-by-one comparison of the state of the address 1 counter and the 4 frame counter. The result of the comparison is recorded in the verifiable chip 15 at the address determined by the address counter 1.

The impulse from the generator 7 by the leading edge gates the comparison unit 5, the unit to the address counter 1 is added along its trailing edge, as a result of which the state of the address counter 1 and the 4 frames counter is first compared, and then appears

new address. I

At the start, both counters are 1 and

4 revoked. As a result of comparing their state, the comparison unit 5 generates a logical unit, which is written to the tested chip 15 at the zero address. Later, as the pulses are received from the generator 7, a non-comparison constantly takes place and at all addresses the zeroes are written to the checked chip 15 . The overflow impulse of the counter 1 of the address overturns the write-read trigger 2, the state of which determines the operation mode of the memory chip 15. Next, the information for all the addresses is mixed. The only e; a; i; nitsa, recorded in the tested chip 15 as a result of this cad

Pa, is entered through the controlled inverter 11 into the counter 12 of the result. In the first cycle, the information passes through the controlled inverter 11, without changing its appearance. At the moment of the end of the reading as a result of the reverse tipping of the trigger 2 of the write-read 2, a unit is recorded in the frame counter 4. When re-recording information is different from that recorded in the previous frame. Since one unit is recorded in the 4-frame counter, the moment of comparison occurs not at the zero address, but at the first one.

Thus, with each new frame of recording information, the address of the unit being written is sequentially increased to 2 -1. After the last frame of write-off of the overflow pulses of the 4-frame counter, the flip-flop 6 is tilted.

Under the influence of the signal from the shutdown trigger 6, the comparison unit 5 generates information that is inverse with respect to that which is output in the first cycle and which is recorded in the tested chip 15,

At each frame of the device, when writing information at 2 addresses, one unit and zeros are recorded in chip 15. During the chip check, the first cycle reads information in 7. frames and, therefore, exactly 2 are received in the result counter 12. units. In the second cycle of operation, the signal from the output of the trigger 6 stop switches the controlled inverter 8 to the inversion mode. As a result, the information supplied to the result counter 12 is exactly the same as in the first cycle. Result counter 12 should have n + 1 bit d. In this case, during the passage of two cycles of operation, in the case of monitoring a working chip 15 at the input of the counter 12, the result receives 2 pulses, it zeroes out and generates an overflow signal.

In the display device, the Pass is illuminated only if by the end of the second cycle of operation exactly 2 Pulses are received at the result counter 12. If at this point, the result counter 12 receives more or less pulses than 2, then the indication lights up.

Marriage. This is achieved by the fact that at the moment of the end of the second cycle, the stop trigger 6 overturns to the initial state, which causes the generator 7 to stop and the single-oscillator 9 to start,

Element I 13 receives a pulse of overflow from the output, counter 12 of the result, which is within the time interval occupied by the pulse from the one-shot 9 (case of checking the serviceable microcircuit). Entry to input Setting to 1 flip-flop 14 of the display, the pulse from the output of the element And 13 tilts it to Goden state, which is immediately indicated by the block 10 of the display.

If a defective chip 15 is monitored and the number of pulses during the whole cycle is tested,

n-f4

the test will be less than 2, then by the time the pulse from the one-shot 9 turns on, the pulse from the output of the result counter 12 is missing, the display trigger 14 remains in the initial state, which is indicated by the signal from the stop trigger 6 ,

If, for any reason, a defective microcircuit generates more pulses than 2 during the full test cycle, the overflow pulse of the result counter 12 appears earlier than the pulse from the single-oscillator 9, the display trigger 14 does not overturn and the state is indicated

Marriage.

Claims (1)

Invention Formula The device dp of controlling integrated memory microcircuits contains a control unit, the first input of which is the information input of the device, the generator whose input is connected to one output of the stop trigger, and the output connected to the input of the sampling signal generator, the output of which is the first control to dim the output of the device, a write-read trigger, one output of which is the second control output of the device, an address counter, the outputs of which are the address outputs of the device, and the outputs of the connecting group The inputs of the second group of the KOTopord are connected to the outputs of the frame counter group, which is due to the fact that, to simplify it, the input of the address counter and the first input of the comparison block are connected to the generator output, the output of the address counter is connected to the write-read trigger, the other output of which is connected to the input of the frame counter, the output of which is connected to the input of the stop trigger, one output of which is connected to the second input of the comparator unit and to the second input of the control unit, and the other output is connected to retim input control unit, an output control unit is a data output device. Compiled by O. Isaev Editor I. Derbak Tehred O. Gortvay Proofreader L. Pilipenko Order 4333/53 Circulation 543 Subscription VNIIPI USSR State Committee for inventions and discoveries .113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4