SU1654824A1 - Device for defect searching - Google Patents

Abstract

The invention relates to means of automatic control and signaling and can be used to detect and diagnose faults in a wide class of control objects. The purpose of the invention is to increase speed by organizing the sequential division in half of the search address space. The device contains two registers, two memory blocks, a clock generator, an indication unit, a comparison unit, a register of successive approximations. 1 il. i (L

Description

The invention relates to means of automatic control and signaling and can be used to detect and diagnose faults in a wide class of control objects.

The purpose of the invention is to increase speed by organizing the sequential division in half of the search address space.

The drawing is given a functional diagram of the device.

The device contains the first 1 and second 2 registers, the first 3 and second 4 memory blocks, the indication unit 5, the clock pulse generator 6, the comparison block 7, and the register 8 successive approximations.

Register 8 consecutive approximations can be implemented on

, IC K155IR17, and Comparison Block 7, having outputs Equal To And Less, on IC K555SP1.

The device works as follows.

The binary signals from the sensors of the monitoring object arrive at the corresponding information inputs of the device and are recorded in the first register 1 at the beginning of each new search cycle. From the outputs of the first register 1, these signals are sent to the second group of inputs of the comparison unit 7, to the first group of inputs of which binary combinations arrive from the outputs of the memory block 3,

corresponding faults. Depending on the result of the comparison, the device may be in one of two possible modes — search or indication.

In the event of a mismatch, the signal at the second output of the comparison block 7 is zero, and the device is in the search mode. In this mode, the register 8 consecutive approximations is in the working state and the second register 2 is disabled. Register 8 of successive approximations operates cyclically, providing a search in the memory of a binary combination matching the input, which is recorded in the first register 1. At the beginning of each cycle, the binary code 011 ... 1 is entered into the register of 8 successive approximations, in which the second 4 and of the first 3 blocks of memory, the fault code and the corresponding combination of binary signals are selected, respectively. If a binary combination is chosen (considered as a binary number) less than the input one, then the first output block Comparing the generated signal 7

ONE LEVEL. THIS SIGNAL AREA-

is taken as the value of the higher bit of the address, because if the binary combination is chosen at the address 011 ... 1, less than the input, the combination matching the input can be found only in the higher memory addresses, for which the value of the higher bit is equal to one. The next pulse arriving at the synchronization of the register of 8 consecutive approximations, this signal from the first output of the comparison block 7 is entered into the highest bit. At the same time, the next, lower order bit is reset to zero. A signal appears at the first output of the comparison block 7, which should be taken as the value of the second-order bit of the address code. The next pulse from the first output of the comparison block 7 is entered into this lower order register 8 successive approximations and is reset to zero is already following it. The process continues, all the address bits will not be formed sequentially in the same way or the binary combination matching the input one will not be found. .If, all address bits specified about

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formed at once, but there is no coincidence; (this happens if the input combination does not match any of the binary combinations stored in the device memory, i.e. in the absence of malfunctions), then the output of the end of the loop of the register 8 consecutive approximations is a zero signal, initiating a new search cycle. At this point, the prohibition of recording the first register 1 is removed and the next sync pulse enters the input combination from the information inputs of the device. By the same clock pulse, the binary code 011 ... 1 is again entered into the register of 8 successive approximations, and the described procedure is repeated.

If at some point the binary combination coinciding with the input one is found, then a second level signal appears at the second output of the comparison unit 7, indicating a fault, and the device switches to the display mode. In this mode, the logical 1 on the prohibition input register 8 consecutive approximations is blocked and allowed to write to the second register 2. In this case, the fault code, which corresponds to the found binary combination, from the outputs of the second memory block 4 is written to the second register 2 and is displayed by the display unit 5. If the malfunction is eliminated and it is required to switch the device back to the search mode, it is sufficient to force the zero input of the first register 1 input. At the same time, the new input combination is written to the first register 1, the logical 1 disappears at the second output of the comparison unit, and the device continues its operation in the search.

Claims (1)

Invention Formula A troubleshooting device comprising two registers, two memory blocks, a display unit, a comparison unit and a clock pulse generator, the group of information inputs of the first register connected to the group of information inputs of the device, the group of outputs of the second register connected to the group of inputs of the display block, and the group of outputs of the first memory block is connected to the first group of inputs of the comparison unit, the group of outputs of the second memory block is connected to the group of informational inputs of the second register, characterized in that in order to increase speed by organizing the sequential division into halves of the address space of the search, a register of successive approximations is entered into it, the output group of the first register is connected to the second group of inputs of the comparison unit, the output is Equal to successive approximations, as well as with the recording resolution input of the first register and is the signal output of the device; the output Less than the comparison unit is connected to the data input of the register of consecutive devices The synchronization input of which is connected to the output of the clock generator; a group of information outputs of the register of consecutive ones:; connected to groups of address inputs of the first and second memory blocks, the output of the clock generator is connected to the synchronous inputs of the second and first registers, the output of the end of the cycle of the register of successive approximations is connected to the input of the prohibition of recording the second register.