SU949822A2 - Rate scaler - Google Patents

Description

one

The invention relates to a pulse technique and can be used in measuring and computing equipment, where the division of pulses, grouped into pulse packets, is required.

According to the main author. St. No. 445162 is known a pulse frequency divider containing a pulse counter, to the outputs of which a switch with two outputs corresponding to the integer and half division factors, as well as the OR element, the And element and the trigger, the first input of which is connected to the switch output of the division factor are connected to the outputs of the decoder. , the zero input of the pulse counter and the first input of the OR element, the second input — with the output of the switchboard half-division factor, and the output through the AND element — with the second input of the OR element 1.

A disadvantage of the known device is low reliability of operation, since the counter can be reset in the process of dividing before the corresponding input pulses expire, and an incomplete reset of the counter is possible, since the duration of the reset pulse is very small.

since it is determined by the transient time in the counter and the decryptor.

The purpose of the invention is to increase the reliability of the device.

5 To achieve this goal, a pulse frequency divider containing a pulse counter, to the outputs of which a switch with two outputs is connected through the decoder

Q for the integer and half division factors, as well as the OR element, the And element and the trigger, the first input of which is connected directly to the output of the integer division factor switch and the first input of the OR element, the second trigger input is connected to the output of the half division coefficient switch, and the output through AND element - with the second input of the OR element, a prohibition element and an additional trigger, the first input of which is connected to

Claims (2)

2Q switch output of the whole division factor, the second input with the zero output of the decoder, and the output with the control input of the prohibition element, the prohibition of which input is connected to the counting input of the tens pulse counter, and the output with the opposite input of the tens pulse counter. The drawing shows a block diagram of the device. The pulse frequency divider contains the driver I of the signal of the end of the packet of input pulses, the counter of 2 pulses, the decoder 3, the switch 4, the triggers 5 and 6, the element AND 7, the element OR 8, the prohibition element 9, the input bus 10 and the output bus 11. The device works in the following way . In the initial state, which is set before the operation of the divider, counter 2, triggers 5 and b are in the zero state, one of the moving contacts of the switch 4 is set to the position corresponding to the selected division factor K, the other to the position corresponding to the half coefficient division. When the input pulses arrive, the counter is filled. 2. After counting 0.5 K pulses at the output of the switch 4, which corresponds to the half division factor, a single level signal appears, according to which the trigger 5 goes into one state. After counting the K pulses at the output of the switch 4 corresponding to the integer division factor, a single level signal appears, which returns the trigger 5 to the zero state. The same signal translates the trigger 6 into one state and through element 8 enters the output bus 11 of the divider. A single signal from the output of the trigger 6 is fed to the control input of the prohibition element 9. Since input pulses arrive at the inhibitory input of this element, at the moment when the Kth input impulse ends, the output of prohibition element 9 results in a unit level signal that sets counter 2 to the zero state. After the counter has arrived in the zero state, a zero level signal appears at the zero output of the decoder 3, which arrives at the input of the trigger 6 and brings it to the zero state. At this point, the first cycle of dividing the input pulses by the number K ends. Further, the operation of the divider is repeated until the packet of input pulses ends. The signal about the end of the packet of input pulses from the imaging unit 1 is fed to one of the inputs of the element 7. If by this time the trigger 5 is in the one state, then the signal from the output of the imaging unit 1 goes through the elements 7 and 8 to the output bus 11 of the divider. Introduction of a second trigger to the pulse divider with separation inputs and a prohibition element ensures the formation of a counter reset signal not earlier than the K th input pulse ends and the counter stops zeroing after its arrival in the zero state. This avoids the operation errors of the divider due to the fuzzy and untimely setting of the divider counter to zero. The invention The pulse frequency divider according to ed. St. No. 445162, characterized in that, in order to increase the reliability of its operation, a prohibition element and an additional trigger, the first input of which is connected to the switch output of the whole division factor, are entered into it, the second input is with the zero output of the decoder, and the output is from the control input of the element the prohibition, the prohibiting input of which is connected to the counting input of the decimal pulse counter, and the output with the embedding input of the ten pulse counter. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 445162, cl. H 03 K 23/04, 1972. 1P P eight Yu / about-