SU947882A1 - Device for identifying object straight edge - Google Patents

Description

The invention relates to automation and computing and can be used in the construction of visual analyzers of robots.

There are known devices for recognizing the right edge of an object, which contain television sensors and electronic components that ensure the selection of useful information from the set of signals that come from the outputs of television sensors Cll. The device for recognizing the right edge of an object, containing serially connected television sensor, is which is connected to the output of the sync pulses of the synchronization unit, and the analog-to-digital converter, the first subtraction unit, the block of elements And, he first, second and third adders 2.

The disadvantages of the known device are low reliability of recognition in conditions of low illumination and exposure to strong interference disturbances, because when exposed to noise, the boundary between the object and the background is blurred. For example, already with a signal-to-noise ratio of 3, the amplitude of the noise emissions becomes comparable with the amplitude of the useful signal from the object. This leads to the fact that already at the stage of localization of contour points, the calculation of the difference of the amplitudes of the unleaded video signal from the output of the television sensor and the delayed video signal delayed by one ra element of the video signal and comparing the result

10 with a limitation threshold preliminarily set in the first threshold element, at its output it forms pulses with pulses whose temporal position does not correspond to the position of the true contour points. In addition, a large number of false contour points from noise spikes exceeding the limitation threshold in the first threshold element occur, as well as significant discontinuities in the contours — in those places where the sum of the signal and noise is in absolute magnitude less than the limitation level. Summation in the first adder of signals that are not contoured leads to errors when determining the direction of the forward edge, as well as to an increase in the probability of false recognition. With a further decrease in the signal-to-noise ratio to unity and less, it is generally impossible to establish a corresponding threshold in the first threshold element and reliably isolate the loop signal and, therefore, recognize the right edge of the object. Here, as in the analogues discussed above, the initial difference in brightness between the object and the background is selected, to find which only the energy of the boundary elements is used, which is extremely insufficient to separate the differential at low signal-to-noise ratios (3). In addition, for recognizing arbitrarily oriented rectilinear elements, device 1 performs a sequential change of the direction of summation by reading in each frame from the memory block to the second and third summers corresponding increments of the X and Y coordinates. When comparing the codes of signals to The output of the count is 1 clock of clock and line pulses, respectively, with the codes of the signals: at the output of the second and third adders, in the comparison circuit, a pulse is produced that opens the element AND If at the moment Meni there is a signal from a contour element at the output of the first threshold element, the signal passes through the open AND gate to the input of the first adder. If there is a linear element in this direction, the signal amplitude in the first adder increases and causes the second threshold element to trigger. Since the recognition process is sequential, it takes considerable recognition time, which increases linearly with increasing sample rate in the directions. A decrease in the sampling rate in the directions leads to a decrease in the reliability of recognition of an arbitrarily oriented direct edge. The purpose of the invention is to increase the authenticity and reduce the time of cognition. . . This goal is achieved by the fact that a device containing a series-connected television sensor, whose input is connected to the output of the sync pulses of the sync block, and an analog-to-digital converter, the first subtraction unit of the And block, the first, second and third adders, is entered into the first multiplication unit, the first division unit, successively connected by the second multiplication unit, the fourth adder, the third multiplication unit, the second subtraction unit and the second division unit, sequentially connected the first quadrant, the fifth sum op, the fourth multiplication unit and the third subtraction unit, also the second quadrant, the fifth and sixth multiplication units and the control unit, the first, second, third and fourth inputs of which are connected respectively to the clock, lowercase, lowercase gass and frame dying pulses the synchronization unit, the first output of the control unit is connected to the gating inputs of the AND block and the first adder, the second output to the synchronization input of the second multiplication unit and to the gating inputs of the second, third and fifth adders, the third high one to the gate input of the fourth adder, the fourth output to the synchronization inputs of the first, third, fourth, fifth and sixth multiplicators, the fifth output to the synchronization inputs of the first and second division blocks, the sixth output to the reset input of the first adder, the seventh output - to the reset inputs of the second, third, fourth and .ptog accumulators, the eighth output to the second input of the fourth and first input of the sixth multiplication unit, the ninth output to the input of the first quad, information input of the third adder, and to the first input the second multiplication unit, the second input of the KOTopoio is connected to the output of the first adder, the output of the analog-digital converter is connected to the information input of the block of elements AND, output of: is connected to the information input of the first adder, the output of which is connected to the information input of the second adder whose output is connected to the first input of the fifth multiplication unit and to the first input of the first multiplication unit, the output of which is connected to the first input of the first Value block, the output of which is connected to the first input of the first block the output of the third adder is connected to the second inputs of the first and third multiplication units and to the input of the second quadr, the output of which is connected to the second input of the third subtraction unit, the output of which is connected to the second inputs of the first and second division units, the second input of the fifth multiplication unit is connected, with the output of the fifth adder, and the output with the second input of the second subtraction unit, the second input of the sixth multiplication unit is connected to the output of the fourth adder, and the output with the second input of the first subtraction unit, in addition the unit y The control unit contains the first horizontal pulse counter, the first counter of continuous pulses, the sequentially included register of X coordinates, the first comparison circuit, the first trigger, the first AND element, the second horizontal pulse counter, the second comparison circuit, the second: the Element I, the first delay element and the first OR element, serially connected register of coordinates Y, the third cf comparison, the second trigger, the third element AND, the second counter of clock pulses, the fourth comparison scheme, the second delay element and the second OR, as well as the register and the third OR element, the first and second inputs of which are the third and fourth inputs of the block respectively, and the output is connected to the second input of the second, OR element and to the reset input of the first clock counter, the count input, which is the first input of the block, and the output connected to the second input of the third comparison circuit, the output of the first horizontal pulse counter is connected to the second input of the first comparison circuit, and the counting input and the reset input are connected respectively to the second and fourth inputs of the block, the second input of the first ele OR is connected to the even-leading input of the block, and the output is the seventh output of the block and connected to the reset input of the second horizontal pulse counter and to the input of setting the first trigger to the zero state, the output of which is connected to the second input of the third And element, the third input of which connected to the first input of the blank, and the output is the first output of the block, the output of the second element OR is connected to the input of setting the second state of the second trigger, to the reset inputs of the second clock pulse counter and is the sixth output of the second block The first input of the element is the second input of the block, the output of the horn is connected to the second inputs of the second and fourth. The comparison circuit is the eighth height of the block, the output of the second horizontal pulse counter is the ninth output of the block, the output of the fourth circuit Comparing the connectors to the second input of the second element AND is the second output of the block, the output of the second element AND is the fourth output of the block, the second output of the first delay is the fifth output of the block, the second output of the second element is the third output of the block. Figure 1 shows the structural diagram of the proposed device; in fig. 2 is a block diagram of the control unit. The device contains a television sensor 1, an analog-digital converter 2, a block of 3 elements And the first adder 4, the second block 5 multiplying, the second adder b, five block 7 multiplying, the first block 8 smart, the first block 9 Subtracting, the first block 10 division unit 11, synchronization unit 11, control unit 12, third adder 13, fifth adder 14,; fourth adder 15, third multiplication unit 16, fourth multiplication unit 17, sixth multiplication unit 18 y, Second multiplication unit 19, first quadr 20, second subtraction unit 21, second quad 22, third subtraction unit 23 Block 12 y the control board (FIG. 2) contains the register of the X coordinate 24, the comparison circuit 25, the first trigger 26, the third element I27, the first element 28, the second counter 29 line pulses, the second comparison circuit 30, the second element 31, the first delay element 32 , the first element OR 33, the first counter of lower case pulses 34, the register 35 of the Y coordinate, the third comparison circuit 36, the second trigger 37, the second counter 38 of the clock pulses the fourth comparison circuit 39, the second delay element 40, the second OR 41, the third OR element 42 , the first counter 43 clock pulses and register 44. Us roystzao works as follows. : Take a look at the operation of the device in detail, and then show the detailed interaction of the blocks included in the device. With the help of block 12, a certain fragment is selected from n n raster elements in the Region of the television image that we are interested in. It is known that the edge of the object is straight; The coordinates of the points belonging to the right edge of the object are interconnected by the linear dependence Y К-Х + 8 where K is the tangent of the angle of inclination B is the free term, but it can be located inside the fragment at any arbitrary angle. We assume that the coordinate system associated with the analysis of the eNbiM fragment is Cartesian, with the origin of coordinates coinciding with the upper left corner of the fragment, the ordinate axis is directed along the horizontal scanning, and the abscissa axis is perpendicular to the horizontal scanning direction. The operation of the device will be considered for the case of two-gradation images, i.e. A / D converter 2 quantizes the signal from the output of television sensor 1 to two levels, for example, to 1 and O, we assume that the sweep is progressive. Spatial summation of the signal from the output of analog-digital converter 2 is performed within the selected fragment along the decomposition line of the television raster. In other words, for each value of X 1, 2, ... n, where X is the current line number within the analyzed fragment, an is the vertical size of the fragment in raster elements, has some accumulated value of the signal YX. Using these data, using linear regression analysis, in particular, the least squares method, one can easily find the parameters K and B 5 of the linear equation, which relates the coordinates of the right edge relative to the adopted coordinate system. The method is based on the choice of such values of K and B, which mini-mise the sum of squares of vertical deviations from the regression line. In other words, the sum S is minimized.

S (Yi - KX - B) 1C

t-l

In relation to the parameters K and B. The extremum is in the usual way, i.e. the derivatives of K and B are taken, equated to zero, and then the expressions obtained are solved together. .After 20 simple calculations, the following expressions are obtained to calculate from the accumulated values of Yx parameters

,; lll. 25

KG

by. , and W Z X)

NO

and about VI - and „1.

1 X Z v - d. Xy z

c-) -1 U. xVI, VI .12.

VI Z X - (2 X) I-1 1

where Ux is the accumulated value of the signals from the output of the analog-digital converter 2 within the horizontal size of the fragment being analyzed in the direction of the horizontal scanning (along the axis of ordinates); X - current line number within the vertical size of the analyzed fragment. Accepts values from 1 to n with the frequency of raz-, screwdrivers;

n - the size of the analyzed fragment, ment in raster elements both horizontally and vertically.

In order for the device to work, it is necessary to ensure its synchronization, i.e. For proper interaction of the entry of the gychi into the device of the blocks, it is necessary to ensure the required time ratios between the control pulses. These functions are assigned to the synchronization unit 11 and the control unit 12. Moreover, block 11 generates the basic sequences of clock pulses for the operation of the television sensor 1 and block 12. In turn, block 12 uses the sequence data, namely clock, lower-case quenching and frame blanking pulses. Forms of units for the units of the device are strokes of strobnavi, dumping and sooiyachatsin: the required time ratios. The device switches to the initial readiness mode on each personnel extinguishing impulse of block 11, the contents of all sugs / pyators are reset, all counters and triggers are set to zero. Frame damping pulses of block 11 are supplied to the second inputs of the first element OR 33 and the third element OR 42. The signal from the output of the first element OR

33 goes to the installation in the zero state of the first trigger 26, to the reset input of the counter 29, to the reset input of the contents of the adder b, the adder 13 of the adder 15 and the adder 14. Signal

from the output of the third element OR 42 to the input of the reset of the first counter 43 and through the second element OR 41 - to the reset of the first adder 4, to the setting of the second trigger 37 to the zero state and to the reset of the second counter 38. The first counter 34 is reset directly by frame suppressants unit pulses 11.

So, let us consider how the summation of signals from the output of the analog-digital converter 2 along the horizontal scanning direction, i.e. obtaining Yx for each value X 1,2, ..., n in expressions for K and B. The coordinates X and Y of the left upper corner of the fragment, relative to the coordinate system associated with the television raster (and, like for the fragment The abscissa axis of the system is also perpendicular, and the ordinate axis along the horizontal scanning direction is entered into the X 24 coordinate register and Y 35 coordinate register. The fragment size in the raster elements is recorded in the register 44 When the signal code from the first output of the horizontal pulse counter is equal

34 with the signal code at the output of the register 24, at the output of the first comparison circuit 25, a signal is generated that translates the trigger 26 into a single state, and the signal from its output will permit the first element 28 and the third element

And 27. At the same time the lower case pulses with., The output of block 11 ,. through the open first element 28 and pass to the first input of the second counter 29, the output of which will be in binary form the signal code corresponding to the values X 1,2, ..., n in the expressions K and B and which changes sequentially with the frequency line scan.

1a the first input of the first element AND 28 is one, the line pulse transfers the second counter 29 to the state X 1. If the code of the signal at the output of the first counter 43 equals the signal at the output of register 35, in the third comparison circuit 36, the pulse the trigger 37 transmits the signal from the output of which is resolving for the third element AND 27. The third element AND 27 performs the function of conjugating three signals. Since the first trigger 26 is also in the single state, i.e., at the second input, the third element And 27 - unit then the clock pulses of the synchronization unit 11 through the third element 27 and pass to the counting input of the second counter 38 and to the gate inputs of the block of elements 3 and the adder 4. The signals from the output of the analog-digital converter 2 through the block 3 pass to the input of the adder 4 (all used accumulator accumulators in the device.) If the signal code from the output of the second counter 38 is equal to the signal at the register output 44, the fourth comparison circuit 39 produces a signal that indicates the end of the fragment horizontally. Thus, at this point in time, for X 1, in the first adder 4 there is an accumulated signal Y, which is then reset by the signal from the output of the second element OR 41 (this signal is generated by the signal from B of the reference circuit 39, which is delayed in the second element 40 delay). The output signal of the second element OR 41 also resets the second counter 38 and sets the second trigger 37 to the zero state. At the same time, at the first input of the third element I 27 is zero, and the clock pulses do not pass through it. The assignment of delays will be explained later.

The next pulse from the output of block 11 through the open element And 28 will set at the output of the second counter 29 a signal code corresponding to X 2. Next, the accumulation occurs in a similar way, i.e. when the code of the signal from the output of the first counter 43 is equal to the signal code at the output of register 35, in the third comparison circuit 36 a pulse is generated which sets the second trigger 37 to one state, and therefore, to the first input of the third element I 27 is one, and since at the second input it is also a unit (the signal from the output of the first trigger 26), then the clock pulses through the open third element I 27 pass to the input of the second counter 38 and to the gate inputs of block 3 and adder 4. Therefore, the signals from the analog-to-digital output The generator 2 passes through the block 3 to the input of the first adder 4. If the signal code at the output of the second counter 38 is equal to the signal at the output of register 44, in the fourth comparison circuit 39 it generates a signal that indicates the end of the sum along the line within the horizontal size analyzed fragment. Thus, at this point in time for X 2, in the first adder 4, the accumulated signal Yj is found, which is then reset by the signal from the output of the second element OR 41. The same signal resets the counter 38 and sets the zero trigger 37 to zero. At the first input of the third element, And 27 is zero, and the clock pulses do not pass to the output. Next, the next line pulse through the open first element And 28 sets the signal code at output 29, corresponding to X 3, the accumulation of signals occurs along this line. The signal at the output of the adder 4 at the end of the accumulation is equal to Yj, and so on, until the code of the signal at the output of counter 29 is equal to the code of the signal at the output of register 44, i.e. when Xn, in this case, a signal is generated at the output of the circuit 30, which indicates the end of the fragment vertically. And when the signals from the output cxeNti 30 coincide with the signal from the output of the fourth comparison circuit 39, a signal appears at the output of the second element And 31, which indicates the end of the fragment, i.e. indicates the lower right corner of the analyzed fragment. This signal, after a delay in the first delay element 32, is used to set the device to the initial state, i.e. it is fed to the input of the first element IL 33, and from its output to the reset inputs of the device blocks. In this case, the second trigger 37 and the counter 38 are set to the zero state by a signal from the output of the second element OR 41 (this signal is generated by the signal of the comparison circuit 39 delayed in the second delay element 40). Consequently, the device is set to the initial state either by the frame extinguishing impulse of the block 11 or by the impulse of the end of the fragment. These signals are collected by OR in the first element OR 33. The first clock counter 43 is reset to the zero state either by a frame damping pulse, or by a horizontal damping pulse. These signals are collected by OR in the third element OR 4 Second trigger 37, second counter 38 clocks and first adder 4. are set to the zero state either by frame extinguishing, or horizontal extinguishing or by the end of fragment fragment horizontally delayed in the second element 40 delays. These pulses are collected by OR in the third element OR 42 and the second element OR 41. So, we looked at how the summation of the signals from the output of the analog-digital converter 2 in adder 4 is considered, otherwise, obtaining Yx for each value X from 1 to n Next, we consider the functions and interaction of the remaining units of the device in accordance with the expressions for K and B. The second multiplication unit performs the multiplication operation by the magnitude of the accumulated signal Yx (X 1,2, .., n), otherwise getting 1 Y , 2- Y ,, ..., п У. This operation is performed on the signal from the output of the fourth comparison circuit 39, i.e. at the end of the summation along the line within the horizontal size of the fragment. This power is supplied to the synchronization input of unit 5 from the output of the fourth comparison circuit 39. The fourth adder 15 performs the operation of summing the products obtained in block 5. The summation is effected by the signal of the fourth comparison circuit 39 delayed in the second delay element 40. This signal is applied to the gate input of the fourth adder from the second output of the second delay element 40. The purpose of the second delay element 40 is the time difference signals of synchronization signals of block 5, which determine the start of the multiplication operation and the gating signals of the fourth adder 15 so that the signal of the gates of the fourth adder 15 appears after performing the alternation operation in the block 5. The purpose of the sixth multiplication unit 18 is to obtain the product of the number n, which in this case determines the fragment size vertically in the raster elements by the accumulated sum of products from the output of the fourth adder 15, and what's the saying getting diminished s L: 1 in the numerator of the expression for the parameter K. The start of the multiplication operation is carried out by the signal from the output of the second element AND 31, i.e. signal end of the fragment. This (the signal is fed to the synchronization input of block 18. The second adder 6 performs the summation of the accumulated values, i.e., m X, -t-D V, V, the Third adder 13 calculates the sum of the X values, i.e. T. X 1 + 2 - (-... + N Kl Information from the output of the adder 4 and the second counter 29 horizontal pulses is recorded respectively into the adder 6 and the adder 13 according to the gating signal from the output of the fourth comparison circuit 39 (at the end of the fragment horizontally) The first multiplier 8 performs the operation of multiplying the signals from the output of the second adder b and the third adder 13, i.e., its output will be a signal that corresponds to the subtracted numerator of the expression for Parameter K. The multiplication operation starts at the signal from the output of the second element I 31 (fragment end signal). This signal is fed to the synchronization input of the first multiplication unit 8. In block 9 the difference of the signals from the output of block 18 and block 9 is calculated to obtain the signal corresponding to the numerator and vi VI jxjIx -IXlVv X-1 X-1 KI-I of the expression for the parameter K. Consider how the signal corresponding to the denominator of the expression dc K and V. Quadrator 20 erect t squared signal from the output of the counter 29, i.e. computes X (X 1, 2,,.., n). The adder 14 g: y emits these signals, i.e. calculates x. . , + n, and the information from the output of the quad 20 is written to the adder 14 by the gating signal from the output of the comparison circuit 39. In block 17, a signal is generated that corresponds to the decreasing p X in the denominator of the expressions for B. In other words, the operation of multiplying the signals from the output of the register 44 and the adder 14 is performed. The multiplication operation starts at the signal from the output of the second element AND 31 (the signal of the fragment fragment. Which is fed to the synchronization input of multiplication unit 17. The second quadrant, 22 squares the signal from the output of the adder 13, i.e., at its output, a signal of BLACK (X) c is formed. the denominator of the expressions for K and B. In block 23, the difference between the signals from the output of block 17 and the signals from the output of quadrant 22 is calculated to obtain the signal code corresponding to the denominator n D x () from the expressions for K and B. And, for 1: in the first block 10, the division; The operation of dividing the signal code corresponding to the numerator is performed (the output of the first subtraction unit 9 by the signal code corresponding to the denominator is the output of the third subtraction unit 23 in the expression for the parameter K. The division operation is performed by the signal from the second output of the first delay element 32, i.e. the delayed signal from the output of the second element I 31, and this signal is fed to the synchronization input of the first dividing unit 10. The delay between the synchronization signal of the multiplication unit 18 and the multiplication unit 17 multiplies €, which determines the start of the operation The multiplication and synchronization signal of the unit 10, which determines the start of the division operation, is performed in the first delay element 32 and a delay is required for the division operation of the beginning to be performed after the execution of the multiplication and subtraction operations. multiplying the signals from the output of the adder 14 and the adder 6, i.e. obtaining a decreasing E, in the expression generator dp of parameter 3. Block 16 performs the operation of multiplying the signals from the output of the adder 13 and the adder 15, i.e. obtaining the deductible numerator of the 15th expression for pars "Letra B. The multiplication operations in blocks 16 and 7 begin to execute according to the signal from the output of the second element (element 31 (fragment end signal)), which is fed to the synchronization inputs of the synchronization blocks 16 and 7 Block 21 calculates the signal difference from the output of block 7 and block 16 to obtain a signal code corresponding to LIO and J-.

 sVy-t xv Z-x expressions for the parameters V, nc, for parameter 19, the parameter B is calculated in block 19, i.e. The code of the signal corresponding to the numerator is divided (the output of block 21 by the signal of the signal corresponding to the denominator (output of block 23). Synchronization 30 and division start is performed by a signal from the second output of the first element 32 delay, which is fed to the synchronization input of block 19. So and the output of block 10 will be a signal code-35a, corresponding to the tangeed angle of inclination of the right edge (k), and the output of block 19 is the signal code corresponding to the free term (B) in the equation Y K X + B relative to the adopted coordinate system , Further on the signals of the end of fragments horizontally with a delay relative to the gating signal of blocks 10 and 19. The device enters the initial readiness mode. Thus, the recognition process for the right edge is completed.

 The inclusion of new units and i. Sv say distinguishes the proposed device from the known. To recognize the right edge, on the one hand, an integral characteristic of the object is used within the object being analyzed (accumulated sums of signal values along the line scan), 55 which makes it possible to fully utilize the energy from the object and, therefore, recognize the right edge at lower signal-to-noise ratios up to one and below, on the other hand, due to the application of a new regression analysis approach to the accumulated data, a high resolution is maintained (estimates of K and B parameters are not placed) and increases the accuracy of determining the direction of the direct edge in the presence of noise. Thus, compared with the known device, it allows to increase the reliability of recognition of the right edge in the signal-to-noise ratio 3. Moreover, since the well-known principle of recognition is used in the known, for checking, for example, thirty directions, thirty frames are required, in the proposed device, the recognition process ends upon completion of scanning of the analyzed fragment, i.e. the required time is less than or equal to the frame time. Thus, the recognition time is reduced by several tens of times, while the structure of the device is simple and easy to implement and it is not necessary to reduce the recognition time to put a large number of devices, each of which is tuned in a specific direction and thereby complicate the structure of the proposed device.

Claims (2)

1. A device for recognizing a direct edge of an object, comprising sequentially combined television sensor, whose input is connected to the output of synchronization pulses of a synchronization unit, and an analog-to-digital converter, a first subtraction unit, a block of elements And, the first, second and third adders, characterized in that , in order to increase the reliability and reduce the recognition time, the first multiplication unit, the first division block, the second multiplication block connected in series, the fourth adder, the third block in multiplications, the second subtraction unit and the second division unit, the first quadrant, the fifth adder, the fourth multiplication unit and the third subtraction unit, as well as the second quadrant, the fifth and sixth multiplication units and the control unit, the first, second, third, and fourth inputs which are connected respectively to the clock, lowercase, lowercase extinguishing and frame extinguishing pulses of the synchronization unit, the first output of the control unit is connected to the gating inputs of the block of elements And and the first adder, the second output - to the input synchronization of the second multiplication unit and to the gating inputs of the second, third and fifth matrices, the third output to the gating input of the fourth adder, the fourth output to the synchronization inputs of the first, third, fourth and sixth multiplication units. the fifth output - to the synchronization inputs of the first and second division blocks; the sixth output - to the reset input of the first master; the seventh output - to the reset inputs of the second, third, fourth and fifth adders, the eighth output - to the second input of the fourth and first inputs of the sixth multiplication unit , the ninth output is to the input of the first quadrant, the information input of the third adder and the first input of the second multiplication unit, the second input of which is connected to the output of the first adder, the output of the analog-digital converter is connected to the information ) 1 entrance to the block of elements I, the output of which is connected to the information input of the first summator, the output of which is connected to the information input of the second adder, whose output is connected to the first input of the fifth multiplication unit and to the first input of the first multiplication unit, the output of which is connected to the first input of the first a subtraction unit, the output of which is connected to the first input of the first division unit, the output of the third adder is connected to the second inputs of the first and third multiplication units and to the input of the second block, the output of which is Inna with the second input of the third subtraction unit, the output of which is connected to the second inputs of the first and second dividing units, the second input of the fifth multiplication unit is connected to the output of the fifth adder, and the output is connected to the second input of the second subtraction unit, the second input of the sixth multiplication unit is connected to the output of the fourth adder, and the output with the second input of the first subtraction unit. 2. The device according to claim 1, characterized by that; that the control unit contains the first horizontal pulse counter, the first clock pulse counter, the sequential-X coordinate register, the first comparison circuit, the first trigger, the first And element, the second horizontal pulse counter, the second comparison circuit, the second And element, the first delay element and the first the OR element, the serially connected register of the Y coordinate, the third comparison circuit, the second trigger, the third AND element, the second clock counter pulse, the fourth comparison, the second element and the second element OR, as well as the register and the third element OR, the first and second inputs of which are respectively the third and fourth inputs of the block, and the output is connected to the second input of the second OR element and to the reset input of the first clock counter, whose counting input is the first input of the block, and the output is connected to the second input of the third comparison circuit, the output of the first horizontal pulse counter is connected to the second input of the first comparison circuit, and the counting input and the reset input are connected respectively to the second and fourth inputs of the block, the second input of the first element OR is connected to the fourth input of the block, and the output is the seventh output of the block and is connected to the i input of the reset second the line pulse counter and to the setup input to the zero state of the first trigger, the output of which is connected to the second input of the third element AND, the third input of which is connected to the first input of the block, and the output is the first output of the block, the output of the second element OR is connected to the installation input in the zero state of the second trigger, with the reset inputs of the second clock counter and is the sixth output of the block, the second input of the first element I is the second input of the block, the register output is connected to the second inputs of the second and fourth That comparison circuit is the eighth output of the block, the output of the second horizontal pulse counter is the ninth output of the block, the output of the fourth comparison circuit is connected to the second input of the second element AND, and is the second output of the block, the output of the second element AND is the fourth output of the block The second output of the first delay element is the fifth output of the block, the second output of the second delay element is the third output of the block. Sources of information taken into account in the examination 1, USSR Author's Certificate No. 548873, cl. G About K 9/00, 1975, 2. USSR author's certificate in application 2815580, cl. G 06 to 9/00 1979 (prototype).