SU941982A1 - Data input/output device - Google Patents

Description

FIELD: telecommunication engineering, telecommunications and can be used in data transmission equipment with digital signal processing.

A device is known that contains a keyboard, the output of which is connected to the input of the encoder, which is connected to the input of the shift register, and the output of the synchronization unit is connected to the input of the first counter I.

The disadvantage of this type of device is the inability to correct the recorded and readable information.

The closest technical solution to the proposed object is the teletape interfacing device CTA-67 with a microprocessor system, which contains a timestamp generator, the first output of which is connected to the third input of a sequential code in parallel, the teletype STA-2MF, the output of which is connected to the first the input of the serial-to-parallel converter and the input are connected by the output of the parallel-to-serial converter; the input of which is connected to the output of the control driver 2 constituent signals.

The disadvantages of the existing devices are low noise immunity, due to the lack of operational control of both the microprocessor n information system entered into the operative memory unit (RAM) and the output information at the terminal (CTA-67), as well as the impossibility of intermediate error correction.

Therefore, the various tasks of developing and debugging prospective 5 devices (in particular, digital conversion devices - signals) require a large and diverse set of auxiliary equipment instead of a single device of operational signaling and interface - UVV.

The purpose of the invention is to increase the reliability of the device.

This goal is achieved by

25 that in a device for inputting and entering water information containing a teletype, the output of which is connected to the input of the first code converter and the first input of the first generator

30 RF tags, the second input of which is connected to the output of the high-frequency generator and the first input of the second time stamp generator, the first output of which is connected to the First input of the second code converter, the first output of the first time information generator, is connected to the second input of the first code converter, a register is entered, the first and the second unit of comparison, the first, second and third generators of single pulses, the first, second, third and fourth switches, the first and second elements And, the first and second counters, the first and the second decoder, output, of the first comparison unit is connected to the first inputs of the first and second switches, the output of the first switch is connected to the first

the output of the device, the output of the first code converter is connected to the second input of the first switch and the first input of the first comparison unit, the second input of which is connected to the second output of the first time stamp generator, the third output of which is connected to the second input of the second switch, the output of which is connected to the first input of the third switch whose output is connected to the input of the first counter and the first input of the first element I, the second input of which is connected to the output of the second element I, whose input is connected to the first input The fourth switch, the output of the first element I is connected to the input of the first generator of single pulses, the output of which is connected to the second output of the device, the output of the first counter is connected to the inputs of the second generator of single pulses and the decoder, the output of which is connected to the third output of the device, the output of the second generator single pulses connected to the input of the second counter, the first output of which is connected to the fourth output of the device, and the second output - to the input of the second decoder, the output of which is connected to the fifth device output, the output of the third generator of single pulses is connected to the second input of the fourth switch, the output of which is connected to the second input of the second time stamp generator, the second output of which is connected to the second input of the third switch, and the third output to the third input of the fourth switch, the input of the second comparison unit connected to the input of the device and the second input of the second code converter, the third input of which is connected to the register output, the output of the second comparison unit is connected to the fourth input v cerned converter i-odov yield kotopoiO soedimen with "swing GSL1T) y1ta.

In the drawing, a block diagram of the device is shown.

The device contains teletype STA-2MF 1, first converter 2 codes, first driver 3 time marks, high frequency generator 4, first comparison unit 5, first switch b, second switch 7, third switch 8, toggle switch Record 9, toggle switch Read 10, first element And 11, the first generator of 12 single pulses, the first counter 13, the first decoder 14, the second generator 15 single pulses, the second counter 16, the second decoder 17, the start button 18, the third generator 19 of single pulses, the fourth switch 20, the Manual 21 toggle switch, Torah timestamp generator 22, the second AND gate 23, the code converter 24 (second), the second comparing unit 25, a register 26, tumbler auto27.

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The device operates in two main modes - write and read - which, in turn, contain manual and automatic modes of operation.

In the recording mode (manual version), the device works as follows.

When the STA-2MF 1 key is pressed, the code sequence of pulses containing two service, four information and one all-auxiliary pulse (seven-bit message) is fed to the first serial-to-parallel code converter 2. The first service start pulse, the code sequence, goes to the first 3 timestamp shaper, to which the main high-frequency pulse sequence from generator 4 is applied. The pulse sequence (starting from the second to fifth, inclusive) received from STA-2MF 1 is written to. the first serial-to-parallel converter 2 is made using synchronization signals, which are 3 timestamps obtained from the first generator. The moments of writing to the first serial to parallel converter 2 are synchronization signals defined by the first driver 3 time stamps are located in the middle of each of the information pulses and the auxiliary pulse. This achieves maximum noise immunity of the recording. At the output of the first converter 2 of a sequential code into a parallel one, the parity of the received five-bit sequence in the first comparison block 5 is performed, which either allows the passage of four informational codes, etc., ii | | (-: rv (tg-o

Converter 2 of the code through the first switch 6 to the memory block, or prohibits it — upon detection of an erroneously received five-bit sequence. An erroneously accepted tibbit sequence is any combination that does not satisfy the parity requirement. The first switch 6 is controlled only after the first comparison unit 5 receives a gating pulse, which allows the parity check result from the comparison block 5 to the first switch 6. From the output of the first switch 6, a four-bit signal in parallel code goes to the first output device connected to the first input of the unit the memory in which the recording is made when the corresponding control signals are formed. An additional signal from comparison unit 5 permits the passage of the four-pulse generated in the first driver 3 through the second switch 7. The output of the second switch. A four-pulse is applied to the third switch 8. The four-pulse passes through the third switch 8 when the enable potential is supplied from the toggle switch. Record 9, toggle switch Read 10 is open. From the output of the third switch 8, the quad permitting pulse is applied to the first element. And, 11 and in the presence of a resolving potential, it launches the first generator of 12 single pulses, forming an impulse. A write strobe applied to the second output of the device connected to the second input of the memory unit. At the same time, the quad pulse from the third switch 8 is fed to the first (decimal) counter 13. The first decoder 14 connected to the decimal counter 13 generates a four select signal, which is fed to the third output of the device connected to the third input of the memory unit. When the decimal counter 13 goes from zero to zero, the second single pulse generator 15 is started, which generates a pulse of the second counter 16 state change (command address), which in the form. The command address is fed to the fourth output of the device connected to the fourth input of the memory block. The three most significant bits, which form the second counter of the address 16 commands, are supplied to the second decoder 17, which generates a chip select signal supplied to the fifth output of the device connected to the fifth input of the memory block.

Thus, to select the four bits of information from the output of the first switch 6, four select signals are generated, as well as command address, chip select, write strobe signals. Directly recording information (4-bit)

carried out by the recording strobe signal.

Automatic recording is performed by turning on the STA-2MF 1 transmitter with punched tape. AT

In this mode, each start pulse synchronously records the required information.

Further, the operation of the device is carried out as previously described.

In read mode, the device performs both manual and automatic control. V. mode. manual (single) reading

Q toggle switch 10 is closed,

and toggle switch Record 9 is open. When the start button 18 is pressed, the positive | LY potential is applied to the three. This generator is 19 single pulses that generates a control impulse arriving at the fourth switch 20. At the same time, the toggle switch Manual 21 is closed. The second time stamp generator 22, which is supplied with high-frequency voltage from generator A, generates a state change pulse, which, if there is a potential to be obtained from a toggle switch, is Read. 10 passes to the input of the first decimal; counter 13.

 The first decoder 14 decrypts the state and generates the signal of the Quartet Choice, which is sent to the memory block. When going first

0 decimal counter 13 from the zero state to one, the second generator of 15 single pulses is started, the pulses of which change

the state of the second counter 16 is the address of 5 commands, information from which is fed to the fourth input of the memory unit. The three most significant bits that are formed by the second counter 16 of the instruction addresses are fed to the second decoder 17, which generates a signal to select a chip fed to the fifth input of the memory unit. The positive potential from the toggle switch. Manual 21 is inverted in the second element AND 23

. and thereby prohibits the passage of a pulse through the first element And 11,

those. The first generator of 12 single pulses does not work, and the write strobe is not applied to the memory block.

0 After all control signals have been established in time: Quadruple selection, Chip selection, Address selection, the second driver 22 timestamp forms

Claims (2)

1. Author's certificate of the USSR 657431, cl. G 06 F 3/04, 1976. 2. Issues of atomic science and nuclear instrumentation   I ki 1979, 3/41, p. 153-166 (prototype)