SU938212A1 - Device for checking electric wiring - Google Patents

Description

The invention relates to measuring technique and can be used to verify the installation of complex electronic devices, electrical harnesses and printed circuit boards during production and operation. ^fifteen

A known device for checking wiring diagrams containing an address allocator, a return address register, a synchronization unit, a print unit, _{) Q is} an address counter that defines and interrogates switches, AND elements [1].

A disadvantage of the known device is the limitation of speed, due to 'successive in vre- ₁₅ Meni polling addresses in inverse controlled points.

The closest technical solution to the invention is a device for monitoring wiring diagrams, comprising a program information input unit, a preprocessing unit, an information distribution unit, asking and asking switches, control units, first and second RAM units, a print unit, analysis units p2j.

A disadvantage of the known device is the low speed due to the need for sequential interrogation of the state of controlled circuits,. carried out in two stages, the first of which checks the health of the circuits provided for by the wiring diagram, and the second checks (searches) the transposition of the conductors, it takes a long time to print the control results. In the known device, the results of the control are sequentially printed out in time for each of the monitored contacts, regardless of whether the result was “Good” or “Bad” for the device for this contact. ‘Another disadvantage of the known device is the low reliability of the control due to the lack of a single generation of the controversial signal for the master and interrogating switch.

9382

Nel invention - improving the speed of the device and the reliability of the control of electrical installation.

This object is achieved in that the apparatus ₅ for kontrolya.elektri- Cesky assembly comprising the print unit, a program information input coupled to an input of the pretreatment unit, the distribution Infor- | _Q mania, whose input is connected to the output pre-processing unit, master and interrogating switches, the control inputs of which are connected respectively through the first and second blocks _{) 5} control with the outputs of the first and second blocks of RAM, the outputs of the master switch and information the inputs of the interrogating switch are connected to the outputs and inputs of the device ₂ θ, respectively, analysis units, the first inputs of which are connected to the outputs of the interrogating switch, the information inputs of the first and second blocks of RAM are connected to the ₂₅ output of the information distribution unit, and their control inputs are connected to the output information processing unit, the first and second reference signal conditioners, the third and fourth RAM blocks, the first and second switches, the first and second are introduced pulse shapers, AND elements, OR element, and group evaluation unit, the output of the first driver of the reference signal being connected to the second ³⁵ inputs of the analysis blocks, the output of the second driver of the reference signal connected to the information input of the master switch and the third inputs of the analysis blocks, fourth inputs ⁴⁰ which are connected to outputs of the third block of memory, the outputs of analysis units are connected to first inputs of respective aND gates to respective first inputs of the second breakers ⁴⁵ and transferred to coo the corresponding inputs of the group evaluation unit, the output of which is connected to the first input of the print unit and to the input of the first switch connected by the first input to the output through the first pulse shaper with the first input of the OR element connected by the second inputs through the corresponding second pulse shapers, with the inputs and outputs of the second - 55 users, the first of which is connected by the second input to the output of the first switch, the last by the output - with the input

4 input blocks of program information, all but the first, with the second inputs with the outputs of the previous switches, the second inputs of which are connected to the corresponding second inputs of the OR element, connected by the output to the second input of the print unit, the third inputs of which are connected to the outputs of the corresponding AND elements, the fourth input - with the output of the fourth memory block connected by information and control inputs with the inputs of the same name of the second and third memory blocks.

The drawing shows a block diagram of a device.

The device comprises a program information input unit 1, an information preprocessing unit 2, an information distribution unit 3, a third 4, a second 5, a first 6 and a fourth 7 blocks of RAM, the first 8 and second 9 control units, specifying 10 and interrogating 11 switches, controlled object 12, first and second 14 reference signal conditioners, analysis units 15, group evaluation unit 16, AND element 17, printing unit 18, switches 19-1 to 19-I, pulse generators 20-120 to h, OR element 21.

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The device operates as follows.

The electrical installation is monitored by sequentially checking all the circuits of the object for the presence of the required connections. Moreover, each time with checking the next chain for availability, they check for the absence of unintended connections with all other chains of the controlled object 12.

In the initial state, there is no program information in the output and buffer registers of blocks 4-7 of the RAM. In accordance with this, control signals from the control unit 9 are not received at the master switch 10. Opened in the initial state, the contacts of the master switch 10 disconnect the driver 14 of the reference signal from the circuits of the controlled object 12. Also, control signals from block 8 are not supplied to the interrogating switch 11. The inputs of the analysis blocks 15 are disconnected from the circuits of the controlled object 12.

During monitoring, the unit 1 for entering program information reads from the program medium, for example, from a punched tape, a program for monitoring a group of chains. The program from block 1 is processed in block 2, where commands are determined that determine the operation mode of the device.

Next, the control program in accordance with the operation mode ^s set in block 2 and the addresses identified in block 3 is allocated by this block to the buffer registers of blocks 4-7.

According to the instructions from block 2, arriving at the control inputs of blocks 4-7, ^10, program information is transferred from the buffer registers to the output registers, freeing the buffer registers for receiving information on monitoring the next group of circuits. The information ^{15 is} received in the buffer registers during the time when the next group of circuits is monitored in accordance with the program located in the output registers of blocks 4-7. ²⁰

The program received in the output registers of block 6 determines the address of the circuit, the presence of which must be checked. In accordance with this program, the control unit 9 provides control signals to the switch 10 ²⁵ for connecting the output of the driver 14 to the selected circuit of the object 12. The program received in the output registers of the unit 4 determines the operation mode of each of the group ³⁰ of analysis units 15.

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In the presence of control circuits operate the same mode of analysis blocks 15 whose inputs are in accordance with my programming ₃₅ are connected through a switch 11 to a circuit which is supplied through the switch 10 from the signal generator 14.

The remaining blocks 15 analysis, being connected through a switch 11 to other circuits of the controlled group that do not have a connection with the specified circuit, operate in the absence of control circuit.

The analysis unit 15, operating in the mode of monitoring the presence of the circuit, compares the signal from the driver 14, which is supplied to its first input, with the same signal received from the driver 14 to the second input through the controlled circuit of the object 12.

If as a result of the analysis it turns out that these signals from the shaper 14 differ by an amount exceeding the permissible, then the block 15 produces an estimate of Wrong. Those of the bays 15, ⁵⁵ that operate in the mode of monitoring the lack of communication compare the signals induced in the controlled circuits (not electrically connected to the circuit to which the signal from the shaper 14 is applied) with the reference signal coming from the shaper 13.

In the case when the signal induced in the controlled circuit through the leakage resistance of the circuit connected to the shaper 14 exceeds the signal from the shaper 13, the corresponding analysis unit will generate a rating of Wicked *. Block 7 provides the storage of information necessary for the forwarding of the numbers of blocks 15, which gave the result 'Bad' * to the constructive addresses of object 12 and to the numbers of its circuits. The deviations from the program assignment identified in the analysis blocks (in the form of 'Negative' ratings) are sent to block 16 of the group assessment, which forms the assessment of the controlled group of circuits.

A group is assessed as unfit if at the output of at least one of the analysis blocks 15 an “Bad” rating is generated. In another case, block 15 forms a “Good” rating. Potential signals Good * and Bad by the output of block 16 are fed to inputs 19-1. The switch 19-1 starts the shaper 20-1. The impulse signal from the shaper 20-1 through the OR gate 21 is fed to the second input of the print unit 18 and allows the registration of the result of the group assessment received from the block 16 to the first input of the print unit 18.

On the trailing edge of the signal from the shaper 20-1, the passage of the Godden or 'Bad sound * signals from the block through switch 19-1 to the input of switch 19-2 is allowed.

The operation of the switch 19-2 - 19- And depends on the presence of the Bad signal at their second input * from the output of the corresponding block 15 (group of blocks).

When there is no such signal, the switch, for example, 19-2 transmits to the output the signal acting on its input, without a delay for the time determined by the corresponding driver 20-2 and does not give a signal to this driver 20-2 "When the specified signal is Failing on the second input of the switch 19-2, the latter issues it to start the corresponding shaper 20-2 without delay, and to the input of the subsequent switch 19-3 with a delay for the response time to the shapers 20-2. Switch 19- b .7 provides a signal to the input of program information input unit 1. On this signal, block 1 provides a transition to the control of the next group of circuits. This ensures that the information in blocks 4 - 7 is rewritten from buffer to output registers, and then control information for the next group of circuits is entered into buffer registers. After the end of the control of all circuits of the object that are not directly connected to the next chain controlled for the presence of connections, they proceed to control the next chain for the presence of the required connections and also check the absence of false connections with the other chains of the object 12.

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In comparison with the known technical solutions, the proposed device provides higher performance - firstly, due to the ability to simultaneously control V "chains in one step (where η is the number of analysis blocks 15 in the proposed device), and secondly, due to ensuring the optimal ratio between the number of measuring channels and the throughput of the recording device, thirdly, in the proposed device, the recording time is made dependent on the number of detected deviations and in their absence, h it is most likely that the time for recording results is minimal.

In addition, in the proposed device, each circuit in the group is controlled by its own analysis unit 15, and the driver 14 is used to generate both the reference and the reference signal, which eliminates the mutual discrepancy between the levels of the reference and the reference signals and provides the proposed device with a higher reliability of control.

Claims (2)

1. Author's testimony of the USSR № 647694, cl. G06 P 15/46, 1976. 2. USSR author's certificate number 559244, cl. G06 F 15/46, 1977 (prototype). And T E