SU746523A1

SU746523A1 - Device for shaping programs for testing wiring

Info

Publication number: SU746523A1
Application number: SU772453829A
Authority: SU
Inventors: Александр Федорович Пименов; Вадим Юрьевич Венцель; Павел Сергеевич Тюхтин
Original assignee: За витель
Priority date: 1977-02-14
Filing date: 1977-02-14
Publication date: 1980-07-07

Description

Изобретение относится к контрольно-¹измерительной технике, может быть использовано в системах автоматическогоThe invention relates to the control- ¹ measurement technology, can be used in automatic systems

' контроля монтажа и неисправностей сложных токораспределйте.льных систем.control of installation and malfunctions of complex current distribution systems.

Известно устройство для обнаружения ⁵неисправностей в электрическом монтаже, содержащее регистратор гальванических связей, первый и второй счетчики, блок вывода, блок ввода, регистр адреса, блок управления, занимающий блок, блок ана- ^,0лиза отказов ζΐ]. .A device for detecting ⁵ faults in electrical installation is known, containing a galvanic connection recorder, first and second counters, an output unit, an input unit, an address register, a control unit, an occupying unit, ana block ^{, 0} failures]. .

Недостатком известного устройства является то, что оно служит только для ₍₅обнаружения неисправностей в монтаже и не может быть использовано для формирования программ контроля.A disadvantage of the known device is that it serves only for ₍₅ detection of faults in the installation and cannot be used to form control programs.

Известно также устройство для проверки монтажа, содержащее блок управления, блоки коммутации, анализа, дешифрации адреса, печати и перфорации, блок ввода информации и блок предварительной обработки [2}.It is also known a device for mounting verification, comprising a control unit, switching units, analysis, address decoding, printing and punching, an information input unit and a pre-processing unit [2}.

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Недостатком известного устройства является то, что оно не исключает повторы на перфоленте в объеме всего контролируемого поля точек. Кроме того, не может быть пригодно как программирующее устройство для любого автомата контроля монтажа.A disadvantage of the known device is that it does not exclude repetitions on a punched tape in the volume of the entire controlled field of points. In addition, it may not be suitable as a programming device for any automatic control of installation.

Целью изобретения являются исключе-’ ние повторов на перфоленте в объеме всего контролируемого поля и использование устройства для формирования программ контроля для любого элемента контроля монтажа, т. е. минимизация формируемой программы.The aim of the invention is to eliminate repetitions on punched tape in the volume of the entire controlled field and to use the device to form control programs for any control element of the installation, i.e., minimize the generated program.

Поставленная цель достигается тем, что в устройство для формирования программ контроля монтажа, содержащее коммутатор, перфоратор, блок управления, первый, второй, третий и четвертый блоки формирования адреса, причем информационные входы коммутатора являются входами устройства, первые выходы первого и второго блока формирования адреса соединены соответственно с первым иThis goal is achieved by the fact that in the device for the formation of the installation control programs containing a switch, a perforator, a control unit, the first, second, third and fourth blocks of the formation of the address, and the information inputs of the switch are the inputs of the device, the first outputs of the first and second block forming the address are connected respectively with the first and

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вторым входом коммутатора, первый и второй выходы коммутатора соединены соответственно с первым входом третьего и четвертого блока формирования адреса, выход блока управления соединен ₅с управляющими входами всех блоков формирования адреса, введены шифратор и блок памяти, причем выход шифратора соединен с входом перфоратора, первые выходы второго, третьего и четвертого Ю блоков формирования адреса соединены соответственно с первым, вторым и третьим входом блока памяти, первый выход третьего блока формирования адреса соединен с третьим входом комму- 15 татора, вторые выходы блоков формирования адреса соединены соответственно с первым, вторым, третьим и четвертым входами шифратора, выход блока памяти соединен с первым входом блока форми- 20 рования адреса, выход блока управления соединен с управляющим входом блока памяти и шифратора. Кроме того, блоки формирования адреса содержат регистр, сдвиговый регистр, счетчик, группу эле- 25 ментов И, элемент ИЛИ и генератор импульсов, причем вход, регистра является 'первым входом блока, выходы регистра соединены с первыми входами соответствующих элементов И группы, выходы эле— 30 ментов И группы соединены с входами элемента ИЛИ и с первым выходом блока, выход элемента ИЛИ соединен с первым входом генератора импульсов, второй вход которого является управляющим вхо- 35 дом блока, выход генератора импульсов соединен с входом сдвигового регистра й счетчика, выход которого является вторым выходом блока, выходы сдвигового регистра соединены со вторым входом 40 соответствующего элемента И группы.the second input of the switch, the first and second outputs of the switch are connected respectively to the first input of the third and fourth address generation unit, the output of the control unit is connected ₅ to the control inputs of all address forming units, the encoder and the memory block are entered, the encoder output is connected to the hammer drill input, the first outputs the second, third and fourth U units of address formation are connected respectively to the first, second and third input of the memory block; the first output of the third address generation unit is connected to the third m input of the switch, the second outputs of the address generation blocks are connected respectively to the first, second, third and fourth encoder inputs, the output of the memory block is connected to the first input of the address generation block, the output of the control unit is connected to the control input of the memory block and the encoder . In addition, the address generation blocks contain a register, a shift register, a counter, a group of 25 AND elements, an OR element and a pulse generator, the input, the register being the first input of the block, the register outputs connected to the first inputs of the corresponding AND elements, the outputs - 30 units AND groups are connected to the inputs of the OR element and to the first output of the block, the output of the OR element is connected to the first input of the pulse generator, the second input of which is the control input of the block, the output of the pulse generator is connected to the input of a shift th counter register whose output is the second output, the outputs of the shift register are connected to the second input 40 and the corresponding element group.

На фиг. 1 представлена блок-схема устройства; на фиг. 2 — функциональная схема коммутатора (коммутатор услов- ₄₅но показан на два входа по т точек в каждом); на фиг. 3 - функциональная схема блока формирования адреса.FIG. 1 is a block diagram of the device; in fig. 2 is a functional diagram of the switch (the switch is conventionally ₄₅ but shown at two inputs with tons of points in each); in fig. 3 is a functional block diagram of the address generation unit.

Устройство для формирования программ контроля монтажа содержит коммутатор 1, _5θблок 2 формирования адреса (входной клеммы), блок 3 формирования адреса (входного разъема), блок 4 формирования адреса (выходного разъема), блок 5 формирования адреса (выходной клеммы), ₅₅блок 6 памяти, шифратор 7, перфоратор 8, блок 9 управления, входы коммутатора 10.1-10.гг), вход блока 11 формирование адреса, выходы 12-13 блока формировния адреса, элементы И'14.1414.пл « элемент ИЛИ 15, регистр 16, сдвиговый регистр 17, счетчик 18, генератор 19, элементы И 20 и ИЛИ 21, группу элементов 22, элемент ИЛИ 23, эталон 24.The device for generating installation control programs contains a switch 1, _5θ , an _{address generation} unit (input terminal), an address generation unit (input connector), an address generation unit (output connector), an address generation unit 5 (output terminal), ₅₅ block 6 memory, encoder 7, perforator 8, control unit 9, switch inputs 10.1-10.yy), block input 11 address generation, outputs 12-13 of the address shaping unit, elements AND 14.1414.pl "element OR 15, register 16, shift register 17, counter 18, generator 19, elements AND 20 and OR 21, group of elements 22, el OR OR 23, standard 24.

Устройство для формирования программ контроля монтажа работает следующим образом. /Device for the formation of control programs installation works as follows. /

В исходном состоянии во всех разрядах регистра 16 блока 3 формирования адреса (входного разъема) записаны 'единички". Количество.разрядов регистра определяется числом входов 10.1-10. гп коммутатора 1. Сигнал из блока 9 управления запускает генератор 19. импульсов блока 3, импульсы с которого поступают в кольцевой регистр 17 сдвига и счетчик 18. Выходы с одноименных разрядов регистров 16 и 17 проходят на входы элемента И 14, сигнал с которого поступает на выход 12 блока 3 и через элемент ИЛИ 15 на запрещаю— · щий вход генератора- 19. Далее сигнал поступает в коммутатор 1 на первый вход группы элементов И 22 и в блок памяти, где формирует адрес считывания. По сигналу из блока 9 управления считывается т -разрядное число и.подается на вход 11 блока 2 формирования адреса (входной клеммы), который аналогично блоку 3 формирует сигнал 12, поступающий на второй вход одного йэ группы элементов 22 и коммутатораIn the initial state in all bits of the register 16 of the address generation unit 3 (input connector) the number one is recorded. The number of register digits is determined by the number of inputs 10.1-10. Gp of switch 1. The signal from control unit 9 starts the generator 19. pulses of unit 3, pulses from which enter the annular shift register 17 and the counter 18. The outputs from the same bits of the registers 16 and 17 pass to the inputs of the element 14, the signal from which goes to the output 12 of unit 3 and through the element 15 to prohibit the The signal then goes to the mmutator 1 at the first input of the group of elements I 22 and into the memory block where it forms the read address.The signal from the control block 9 reads a t-digit number and is fed to the input 11 of the address formation block 2 (input terminal), which, similarly to block 3, forms signal 12 arriving at the second input of one ye group of elements 22 and the switch

1. Выход элемента И 22 через эталон 24 поступает на один из входов группы элементов И 20 коммутатора и через элемент ИЛИ 23 на вход 11 блока 4 формирования адреса (выходного разъема), который также формирует сигнал 12, поступающий на второй вход группы элементов И 20 и одновременно в блок 6 памяти, где формирует адрес записи. Выходы элементов И 20 коммутатора через элементы ИЛИ 21 поступают на вход 11 блока 5 формирования адреса (выходной клеммы), выходной сигнал 12 которого приходит в блок 6 памяти, образуя число записи. Это число по сигналу блока 9 управления по вышесформированному адресу записывается в блок 6 памяти, Выходы 13 блоков 2-5 формирования адреса через шифратор 7 последовательно подаются на перфоратор 8. После окончания перфорации цикл формирования адреса продолжается: в блоке 5 по сигналу блока 9 управления продвигается.'единичка' в регистре 17, формируется сигнал 12 и т. д. При продвижении сигнала оп5 7465231. The output of the element And 22 through the standard 24 is supplied to one of the inputs of the group of elements AND 20 of the switch and through the element OR 23 to the input 11 of the address generation unit 4 (output connector), which also generates a signal 12 that arrives at the second input of the group of elements AND 20 and simultaneously in memory block 6, where it forms the address of the entry. The outputs of the elements And 20 switch through the elements OR 21 are fed to the input 11 of the block 5 forming the address (output terminals), the output signal 12 of which comes in the memory block 6, forming the number of entries. This number is written to the memory block 6 by the signal of the control block 9 at the above address. Outputs 13 of the address shaping blocks 2-5 through the encoder 7 are successively fed to the perforator 8. After the punching is completed, the address formation cycle continues: in block 5, the control block 9 advances . 'unit' in register 17, a signal 12 is formed, etc. When the signal advances op5 746523

роса до блока 3 формирования адреса , (входного разъема) из блока 6 памяти в блок 2 формирования адреса (входной клеммы) по входу 11 считывается число, уже откорректированное предыдущим 5 опросом, это исключает появление повторов на перфоленте в объеме всего контролируемого поля.dew to block 3 forming the address (input connector) from block 6 of memory to block 2 forming the address (input terminal) input 11 reads the number already corrected by the previous 5 surveys, this eliminates the appearance of repetitions on punched tape in the volume of the entire controlled field.

Применение устройства позволяет исключить повторы на перфоленте в объеме · Ю всего контролируемого поля, т. е. минимизировать программу, а также формировать программу по эталону для любого автомата контроля монтажа.The use of the device allows you to exclude repetitions on a punched tape in the volume · S of the entire controlled field, i.e., minimize the program, and also formulate a program according to the standard for any automatic device for controlling the assembly.

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Claims

I. . The invention relates to measurement instrumentation, can be used in systems for automatic control of installation and for malfunctions of a complex current distribution system. A device for detecting electrical installation faults is known, which contains a galvanic communications recorder, first and second counters, an output unit, an input unit, an address register, a control unit, an occupying unit, a failure analysis unit W.W. A disadvantage of the known device is that it serves only to detect faults in the assembly and cannot be used to form control programs. It is also known a device for checking an assembly, comprising a control unit, switching units, analysis, address decoding, printing and punching, an information input unit and a preprocessing unit 1SC. A disadvantage of the known device is that it does not exclude repetitions on a punched tape in the volume of the entire controlled field of points. In addition, it may not be suitable as a programming device for any automatic control of installation. The aim of the invention is the elimination of repetitions on punched tape in the volume of the entire controlled field and the use of a device for forming control programs for any element of the assembly control, i.e. minimization of the formed program. The goal is achieved in that a device for generating assembly control programs comprising a switch, a perforator, a control unit, first, second, third, and fourth address generation units, the switch information inputs being device inputs, first outputs of the first and second address generation unit connected to the first and second input of the switch, respectively; the first and second outputs of the switch are connected respectively to the first input of the third and fourth address generation unit; output of the switch The control unit is connected to the control inputs of all address generation units, an encoder and a memory unit are inserted, the output of the encoder is connected to the input of the perorator, the first outputs of the second, third and fourth address formation units are connected to the first, second and third memory blocks, respectively. ti, the first output of the third address generation unit is connected to the third input of the switch, the second outputs of the address generation units are connected respectively to the first, second, third and fourth inputs of the encoder, the output of the memory block and connected to the first input of the address generation unit, the output of the control unit is connected to the control input of the memory unit and the encoder. In addition, the address generation blocks contain a register, a shift register, a counter, a group of AND elements, an OR element and a pulse generator, the input, the register being the first input of the block, the register outputs being sinned with the first inputs of the corresponding AND elements, the outputs of the AND elements the groups are connected to the inputs of the OR element and to the first output of the block, the output of the OR element is connected to the first input of the pulse generator, the second input of which is the control input of the block, the output of the pulse generator is connected to the input of the shift register and a counter, whose output is the output of the ring W, the shift register outputs are connected to a second input of the respective AND gate group. FIG. 1 is a block diagram of the device; in fig. 2 - functional diagram of the switch (the switch is conventionally shown at two inputs with m points in each); in fig. 3 - functional unit for the formation of the address. The device for 4 p1 iravnogo of the installation control software holds the switch unit 2 forming the address (input terminal), block 3 forming the address (input connector), block 4 forming the address (output connector), block 5 forming the address (output terminal), unit 6 memory TI, encoder 7, perforator 8, control block 9, switchboard inputs 10.1-10.tt), block 11 input is formed of addresses, addresses form 12-13 of the address shaping block, elements H14.1-fl4.nn, element OR 15, register 16, shift register 17, counter 18, generator 19, elements AND 20 and OR 21, group of elements 22, element OR 23, fl Alon 24. A device for generating assembly control programs works as follows. In the initial state, in all bits of the register 16 of the address formation unit 3 (input connector), ones are recorded. The number of register bits is determined by the number of inputs 10.1-10. hp switch 1. The signal from control block 9 starts the generator 19. pulses from block 3, the pulses from which are sent to the ring shift register 17 and the counter 18. The outputs from the same bits of registers 16 and 17 pass to the inputs of the And 14 element, the signal from JKOToporo enters output 12 of block 3 and through the element OR 15 to the inhibitory input of generator 19. Next, the signal enters switch 1 at the first input of the group of elements AND 22 and into the memory block, where it forms the readout address. The signal from control block 9 reads an m-bit and is fed to input 11 of address formation block 2 (input terminal), which, similarly to block 3, generates a signal 12 fed to the second input of one of the group of elements 22 and switch 1. Output of element 22 through the standard 24 goes to one of the inputs of the switch element group AND 20 and through the OR element 23 to the input 11 of the address formation unit 4 (output connector), which also generates a signal 12 that arrives at the second input of the group of elements AND 2O and simultaneously to the memory block 6 tee where you form t address of the entry. The outputs of the switch elements AND 20 through the elements OR 21 are fed to the input 11 of the address shaping unit 5 (output terminal), the output signal 12 of which arrives at the memory unit 6, forming the record number. This number is written to the memory block 6 by the signal of the control unit 9 at the above address. The outputs 13 of the address shaping unit 2-5 through the encoder 7 are successively fed to the perforator 8. After the completion of the perforation, the address formation cycle continues: in block 5, the unit in the register 17 advances along the signal of the control unit 9, the signal 12 is generated, and so on. polling before the address formation block 3, (input connector) from memory block 6 to address shaping block 2 (input terminal) input 11 reads the number already corrected by the previous survey, this eliminates the appearance of repetitions on punched tape in the amount of all its controlled gender. The use of the device allows you to eliminate repetitions on a punched tape in the volume of the entire controlled field, i.e., minimize the program, and also formulate a program according to the reference standard of any automatic machine for control of the installation. Claim 1. A device for generating assembly control programs comprising a switch, a perforator, a control unit, the first second, third, and fourth address-shaping units, the information inputs of the switch are the inputs of the device, the first outputs of the first and second address generation units are connected respectively, with the first and second inputs of the switch; the first and second outputs of the switch are connected respectively to the first input of the third and fourth address generation unit; the output of the control unit with Dinen with control inputs of all address formation blocks, characterized in that, in order to minimize the generated program, an encoder and a memory block are inserted into the device, the encoder output is connected to the perforator input, the first outputs of the second, third and fourth address formation blocks are connected respectively7, 236 with the first, second and third inputs of the memory unit, the first output of the third address generation unit is connected to the third input of the switch, the second inputs of the address generation units are connected respectively to the first , Second, third and fourth inputs of the encoder, the output memory unit is connected to a first input address generating unit, the control unit output is connected to the control input of the memory and the encoder. 2, the device according to claim 1, wherein the address generation unit comprises a register, a shift register, a counter, a group of elements. AND, the OR element, and. a pulse generator, the register input being the first input of the block, the register outputs connected to the first inputs of the corresponding AND elements of the group, outputs AND elements of the group connected to the inputs of the OR element and to the first output of the block, the output of the OR element connected to the first input of the impulse generator, the second the input of which is the control input of the block, the output of the pulse generator is connected to the input of the shift register and the counter, the output of which is the second output of the block, the outputs of the shift register are connected with the second input to corresponding element AND group. Sources of information taken into account during the examination 1. USSR author's certificate No. 490123, cl. Q QP 11/00, 03/09/73,

2. USSR author's certificate number 4O4056, cl. Q 05 23/02 (prototype).

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