SU928276A1 - Frequency discriminator - Google Patents

Description

I

The invention relates to radar and communication technology and can be used in devices measuring the frequency of radio pulse signals reflected from extended objects, such as meteorizations.

A frequency discriminator is known, comprising a limiter, a generator, a phase shifter and the first and second channels, each of which contains a first multiplier, a drive and a series-connected phase detector, an analog-to-digital converter, a memory unit, a second multiplier and an addition unit, while the limiter output is connected with the first inputs of the phase detectors of the first and second channels, the output of the generator is connected to the second input of the phase detector of the second channel directly, and to the second input of the phase detector channel through the phase shifter, the output of the memory block of the first channel is connected via

the first multiplier of the first channel with the second input of the second channel addition unit, and the output of the second channel's memory block are connected via the first multiplier of the second channel to the second input of the adder of the first channel 11.

However, the known frequency discriminator has a low sensitivity.

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The purpose of the invention is to increase the sensitivity.

To achieve the goal, a frequency discriminator containing a limiter, oscillator, phase shifter and

IS first and second channels, each of which contains a first multiplier, a drive and a series-connected phase detector, analog-to-digital converter, block

20 memory, the second multiplier and the addition unit, while the output of the limiter is connected to the first inputs of the phase detectors of the first and second 3 channels, the output of the generator is connected to the second input of the phase detector of the second channel directly, and to the second input of the phase detector of the first channel through a phase shifter, the output of the memory block of the first channel is connected via the first multiplier of the first channel to the second input of the second channel addition block, and the output of the memory block of the second channel is connected via the first alternator of the second channel c to the first input of the first channel addition block, the first and second number registers, the subtraction block, and the first subtractor block, the combining block and the second and third subtractor blocks connected in series, are inserted into each I channel, with the same input of the second and third blocks in each channel the subtraction unit is interconnected, the output of the addendum unit is connected to the input of the accumulator through the successively connected first block in the reading and the combining unit, the output of the analog-to-digital converter is connected to the second inputs of the first and third the subtraction units, the outputs of the first and second channel accumulators are connected to the same inputs of the subtraction unit, the third subtraction output of the first channel is connected to the second input of the second channel combiner, the output of the third second channel subtractor is connected to the second input of the first channel combiner block, and the second the inputs of the same multiplier of each channel are interconnected and with the output of the register of the same name. FIG. 1 shows a structural electrical circuit of the device; FIG. 2 is a static characteristic of the proposed device (/ sf T is the nominal value of the detuning frequency},). The frequency discriminator contains limiter 1, generator 2, phase shifter 3, first and second registers and 5 numbers, subtraction unit 6, first and second channels 7 and 8, each of which contains phase detector 9, analog-digital converter 10, memory unit 11 The first multiplier 12, the second multiplier 13, the addition unit 14, the first, second and third subtractors 15-17, the combining unit 18 and the accumulator 19 The frequency discriminator works as follows. Signals from extended objects with carrier frequency F are fed to the input of limiter 1, in which the dynamic range of the original signals is compressed. The quadrature components of the signal from the output of phase detectors 9 are fed to analog-to-digital converters 10, where they are quantumized in time and amplitude. In this case, the second inputs of the phase detectors 9 from the generator 2 directly and through the phase shifter 3 receives the signal of the reference frequency fo. The digital codes of the quadrature components x detained in the memory blocks 11 for the interval T. (first channel 7}, CC-T (second channel 8) arrive at the first inputs of the first and second multipliers 12 and 13. The first and second registers and 5 numbers store the values of 51 and 8 respectively. As a result of the operations in the first and second multipliers 12 and 13 and the addition unit 14 and the second subtraction unit 16 a two-dimensional rotation of the quadrature components at angles of 0 and 9 occurs. from the outputs of analog-c of the transducers 10. As a result, the inputs of each block 18 of the union form the URI values Xn, -Slk, n COSe- y K - I Sin0) j 1) m Uk- (UkN COSe-Av -i Slnd) for the first channel 7 and ikg ".- (C0" 9 -Uk-,),, 1) k2-Uk- (Uk-1C059) for the second channel 8. In block 3, 18, the values for the first channel are calculated 7 voy: g 2dl of the second channel 8. In accumulators 19, data is accumulated from N adjacent elements of the range resolution, which allows smoothing out fluctuations of incoming signals and reducing the effect of internal receiver noise. After subtracting, the output of block 6 produces the value

hkg, which depends on the magnitude. derangements f,

The static characteristic of the discriminator is

Mr.Nosin () () lY

Characteristics of the proposed discriminator when shown in figure 2. The dotted line corresponds to the known device

The steepness of the characteristics of the proposed frequency discriminator within the linear section is l,, 8 times higher than that of the Known, which is equivalent to a corresponding increase in sensitivity.

1) formula of the invention. A frequency discriminator comprising a limiter, a generator, a phase switch (the first and second channels, each of which contains a first multiplier, a drive and a series-connected phase detector, analog-to-digital converter, memory block, second multiplier and addition block, the output of the limiter is connected to the first inputs of the phase detectors of the first and second channels, the output is connected to the second input of the phase detector of the second channel directly, and to the second input of the phase etektora first channel - via a phase shifter, the output of unit memory of the first channel is connected via a first multiplier the first channel to the second block the second input of adder

channel, and the output of the second channel memory block is connected via the first multiplier of the second channel to the second input of the first channel addition block, characterized in that, in order to increase the sensitivity, the first and second number registers are entered, the subtraction block, and the first block in each channel the subtractor, the combining unit, and the successively connected second and third subtractors; in each channel, the same inputs of the addition unit and the second subtraction unit are interconnected, the output of the addition unit is connected to the input of the accumulator via Then the first subtractor and the combining unit are connected, the output of the analog-digital converter is connected to the second inputs of the first and third subtractors, the outputs of the accumulators of the first and second channels are connected to the same inputs of the subtraction unit, the output of the third subtraction unit of the second channel channel, the output of the third subtraction unit of the second channel is connected to the second input of the first channel combining unit, and the second inputs of the same multipliers of each channel connected to each other and with the release of the same number register.

Sources of information taken into account in the examination

1. USSR author's certificate (f, cl. G 01 S 7/36, 19.03-77 (prototype).

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Claims (1)

Claim A frequency discriminator comprising a limiter, a generator, a phase shifter, and first and second channels, each of which contains a first multiplier, a drive, and a phase detector, an analog-to-digital converter, a memory unit, a second multiplier, and an addition unit, the limiter output being connected to the first ones the inputs of the phase detectors of the first and second channels, the output is generator-connected to the second input of the phase detector of the second channel directly, and with the second input of the phase detector of the first channel - through the phase shifter, the output of the memory channel of the first channel is connected through the first multiplier of the first channel to the second input of the addition unit of the second 928276 is 6 channels, and the output of the second channel memory block is connected through the first multiplier of the second channel to the second input of the addition channel block of the first channel, characterized in that, in order to increase the sensitivity, the first and second number registers, a subtraction block, are introduced, and in each channel - the first subtraction unit, the joining unit, and the second and third subtraction units connected in series, while in each channel the inputs of the addition unit and the second subtraction unit are connected, the output of the addition unit is connected to the drive input after The first subtraction unit and the combining unit included, the output of the analog-to-digital converter 20 is connected to the second inputs of the first and third subtraction units, the outputs of the drives of the first and second channels are connected to the inputs of the subtraction unit of the same name, the output 25 of the third subtraction unit of the first channel is connected to the second input of the unit combining the second channel, the output of the third subtraction unit of the second channel is connected to the second input of the jo block joining the first channel, and the second inputs of the same multipliers of each channel with dineny between themselves and with the output of the register the same name.