SU924753A1 - Ferrite core storage device - Google Patents

Description

The inputs of which are connected to the outputs of the address and address-bit drivers The inputs of which are connected to the outputs of the address and address-discharge decoders of the first stage, the inputs of which are connected to the outputs of the address and address-discharge pierHCTpoB, respectively, are connected to the address buses, address The address code replication code is connected to the nth input of the address da- encoder of the first stage, and the output of the address register from the second to Sr CONNECTIONS to the inputs of the address decoder of the first stage from the first to (tl-I) and. FIG. 1 shows a diagram of the proposed device in FIG. 2 - single bit drive firmware diagram. The device comprises a storage unit 1, an address unit 2 of second-stage decoders, an address-discharge unit 3 of second-stage decoders, an address unit 4 of the forcing pulse formers, an address-discharge unit of the 5 formers of pulse. current, address block 6 first-stage decoders, address-discharge bls 7 first-decoders, steps, acres register 8 for P bits, arousal-raer dan register 9 for hl bits, address reception bus 10, address register decodes ± 1 - 11, the inputs of the address block of the first-stage decoders 12 12fi outputs of the address block of the second-stage decoders, the outputs a {H of the light-discharge register l4 -14rn ,. the inputs of the address-discharge unit of the decoders, the first stage, the outputs of the address-discharge unit of the second-stage cscherfritors, the address-relay of the storage winding, the address storage of the storage IS. windings: address-bit 17, -17 || P, to which the same-named outputs 16–16 "ayresno-razr dnggo block d isffratorov second stage 3, and address ia) -18j, n, to which one nominal output address block Stage 2. The outputs of the address-bit repngra 9 are connected to the same-name inputs of the address-bit block 7 of the first-stage decoders. The outputs of the address register 8 are connected to the inputs of the first-stage 6 decoders block as follows: the output of the first (low) bits of the address register 8 is connected to the input 12 of the last (most-significant) bits of the address block 6 of the first-stage decoders, outputs from the second to and -and address Register 8 is connected to the inputs from the first to (p-1) -th efficient de-encryption block of the first stage 6. Due to this, the connection of the .aarest register with the address unit of the first-stage decoders when supplying consecutive addresses to the address register dresnye winding selected alternately left and right of overlapping output winding. The device works as follows. Assume that the selected array has addresses from 18 -18, and for storing the array array in question, cores are used that are located at the intersection of the winding of the 17th windings 18jj. When addressing this array, address windings 18 -l8 are selected (. 18. Jaa7i ) 183, 18 (2 ,,) 18.0, with each address winding selecting an address-discharge of the bottom winding I7t. This sequence of sampling the address windings is repeated for any selected address-bit winding. Let us estimate the value of that component of the interference from the half-selected cores, which is associated with the non-identical states of compensating each other pairs of half-selected cores located on opposite sides of the cross. Interference from the half-selected cores occurs when they are influenced by a read current pulse in only one of the coordinates / and the cores in the 5ns unit state and the destroyed zero give a big hindrance. Compensation of these interferences is ensured by flashing the outgoing winding with direct and reverse power intersection, and net compensation (total interference close to zero) is provided% if there is an equal number of cores producing large interference in the Compensating segments of the output winding and there is little interference. After supplying the read current, for example, to the winding 17, all the cores of this winding are in the states of a destroyed unit or in each other zero, i.e. when you read everything

they are subject to disturbance and provide the best compensation. If, after this, a reference to a certain array begins and the 17c winding is repeatedly selected, then. on the cores of the winding 17 |. current pulses in the windings of NW, l8t2 (iM); : isj / i.e., jn / b + j), etc., after which the corresponding interceptors remain in the unit or zero state, i.e. tfi following treatment they give a big hindrance. Since the supply of tokas to the winding 18 in the proposed device is performed alternately - first into one winding KU to the left of cross wires of the Bbucoff winding, then into one winding from cross wires of the output about & hanks, etc., the maximum total interference from the first call to the winding 17j, differs from the blind in the best compensations only by the magnitude of the difference between large and small noises from one pair of cores. A similar effect is also achieved in all cases of d4, for example, if, before addressing it to a given array, an impulse is sent to the array under consideration.

Thus, in the proposed device, we consider the composition of the signal, due to interference from the populated cores, by the address-discharge windings decreased by a factor of 1, and by address windings by a time. For modern mass storage systems of the 2.5D system, the values of 2 and 2 are 256 512 and 32-64, respectively, therefore, in the proposed device, the total is reduced several times. This allows cj to significantly increase reliability (the likelihood of a device failing

or increase the speed of the device by 1-2-2 times by reducing the attenuation time of the interference.

Formula inventions

A memory device on ferrigovy sickles that support HaKototTenb, fulfilled in c {theme; 2.5D, the inputs of which are connected to the outputs of the address and address-discharge decoders of the second stage, the inputs of which are connected by the No.Y to the outputs of address and address formers, the inputs of which are tailored to the outputs of the address and address-resolution of the first-stage decoders, the inputs of which are connected to the outputs of the address and address-bit registers, respectively, the inputs of which are connected to the address of the To increase the reliability of the device, in it the first output of the address register is connected to the input of the address decoder of the first stage, where rm is the number of bits of the address register, and the outputs of the address register from the second to n are connected to the inputs of the address decoder of the first stage from the first to -1), respectively.

Sources of information taken into account in the examination

1. Storage device up to 3UBMi Sat. articles ed. Krupsky A. A. M., Mir, 1968, p. 56.

2. Shigin, A.G. and Deryugin, A.A. Digital Computers, M., Energie, 1975, p. 161 (prototype).

i

JU

I -; v - 41

I

 l

f “v

t

IE

 . fgf ... 18 n / ... I8i 181

Claims (1)

Claim A storage device on ferrite cores, containing a drive made according to the 2.5D system, the inputs of which are connected to the outputs of the address * and address-bit decoders of the second stage, the inputs of which are connected to the outputs of the address and address-bit shapers, the inputs of which are connected to the outputs of the address and address-bit decoders of the first stage, the inputs of which are connected to the outputs of the address and address-bit registers co. responsibly, the inputs of which are connected to the address lines, which distinguishes from I * in that, in order to increase the reliability of the device, it first output connected to the address register _p 2mu entry address decoder of the first stage, where rm. —The number of bits of the address register, and the outputs of the address register from the second to the ηth are connected to the inputs of the address decoder of the first stage from the first to (n-1) th, respectively.