SU921096A1

SU921096A1 - Gated frequency divider

Info

Publication number: SU921096A1
Application number: SU802949369A
Authority: SU
Inventors: Авадий Матвеевич Гамбург; Евгений Константинович Иосипов; Михаил Константинович Солоха; Леонид Моисеевич Фельдман
Original assignee: Предприятие П/Я А-7133
Priority date: 1980-07-02
Filing date: 1980-07-02
Publication date: 1982-04-15

Description

(54) СТРОБИРУЕМЫЙ ДЕЛИТЕЛЬ ЧАСТОТЫ(54) PLANNED DIVIDER OF FREQUENCY

1one

Изобретение относитс к импульсной технике .The invention relates to a pulse technique.

Известен делитель частоты с прив зкой сигналов к задающей частоте, содержащий последовательно соединенные триггеры со счетным входом, логический элемент И-НЕ, элемент ИЛИ-НЕ, дополнительный триггер и дополнительный элемент И-НЕ, выход которого соединен с одним входом элемента , второй вход которого подключен к выходу основного элемента И-НЕ 1.A known frequency divider with signal coupling to a master frequency, containing series-connected triggers with a counting input, an AND-NOT logic element, an OR-NOT element, an additional trigger and an additional IS-NOT element, the output of which is connected to one input of the element, the second input of which connected to the output of the main element AND-NOT 1.

Данный делитель не обеспечивает достаточной точности делени .This divider does not provide sufficient division accuracy.

Наиболее близким по технической сущности к изобретению вл етс делитель частоты , содержащий последовательно включенные каскады делени , логические цепи, причем на входы каскадов-делени поданы стробирующие сигналы 2.The closest in technical essence to the invention is a frequency divider containing sequentially connected division cascades, logical circuits, with the strobe signals 2 being fed to the inputs of the cascade-division.

Данный делитель не обеспечивает достаточной точности временных прив зок за счет нестабильности задержки выходных импульсов по от 1ошению к стробирующему.This divider does not provide sufficient accuracy of time bindings due to the instability of the delay of the output pulses from 1 to the gate.

Целью изобретени вл етс уменьшение нестабильности задержки выходных импульсов по отношению к стробирующему.The aim of the invention is to reduce the instability of the delay of the output pulses with respect to the gate.

Поставленна цель достигаетс тем, что в стробируемый делитель частоты, содержащий m каскадов делени частоты, вход первого из которых соединен с входной шиной , а входы управлени всех каскадов делени частоты соединены с шиной стробирующего сигнала, введены блок задержки и элемент ИЛИ, входы которого соединены с выходами всех каскадов делени частоты кроме последнего, а выход подключен к входу последнего каскада делени частоты, входы всех каскадов делени частоты, кроме первого и последнего, соединены с выходами блока задержки, вход которой соединен с входной шиной.The goal is achieved by the fact that a gated frequency divider containing m frequency division cascades, the input of the first of which is connected to the input bus, and the control inputs of all the frequency division cascades are connected to the gate signal bus, a delay block and an OR element, whose inputs are connected to the outputs of all stages of frequency division except the last, and the output is connected to the input of the last stage of frequency division, the inputs of all stages of frequency division, except the first and last, are connected to the outputs of the delay unit, the input which is connected to the input bus.

На чертеже приведена структурна электрическа схема предлагаемого делител частоты.The drawing shows a structural electrical circuit of the proposed frequency divider.

Делитель частоты содержит каскады 1-4 делени частоты, блок задержки 5, элемент 6 ИЛИ. На входную шину 7 подаетс входной сигнал, а на шину 8 - стробирующий сигнал.The frequency divider contains cascades 1-4 frequency division, delay unit 5, element 6 OR. An input signal is supplied to the input bus 7, and a strobe signal is fed to the bus 8.

Принцип работы делител заключаетс в следуюшем.The principle of operation of the divider is as follows.

Claims

In the initial state, at the moment of time t o the work of the divider is forbidden by the low (zero) potential arriving via the pin 8 (there is no gate). There are no pulses at the output of the divider, since all the division cascades are set to the zero initial state by low potential and their work on pulse division is prohibited for the time of the absence of the gate. Bus 7 contains input pulses that go to the first cascade of division 1, without changing its state, and to the delay unit. which forms at its outputs the pulses delayed relative to the input pulses, respectively, by 1/3 Tvh and 2/3 Tvh, where Tvh is the period of the following impulses. The pulses from the outputs of the delay unit, respectively, arrive at the inputs of stages 2 and 3 of the frequency division, without changing their state. When entering at time t2 along the gate 8 of the gate with a high level potential, the work on the division of pulses in frequency division cascades is permitted. Frequency division cascades operate on the leading edge of positive pulses. Thus, at time t2, the first cascade of division does not switch over the pulse arriving on bus 7 at time tj, since time tt is ahead of time t2. The first switch is a division 2 stage, to the input of which at time tj a pulse delayed with respect to the strobe comes from the output of the delay unit. Positive voltage difference from the output of division stage 2 through element 6 enters the input of the second division stage and switches it. At the output of the divider, a high level potential appears. Then, at the instants of time t and ts, respectively, the division stage 3 and division stage i occur, and, at times, t,., Tg, the stages 1–3 division are turned off. At the inputs of element 6 and, therefore, at its output at time t, a low level potential is established. When the next pulse arrives at time t, a high level potential is established again at the output of cascade 2 of dividing line at its output, which through element 6 enters the dividing stage 4 and switches it to the zero state. Thus, at the output of element 6, positive pulses are formed with a 2 Txx following period and with an instability delay relative to the strobe, since with an arbitrary arrival time of the strobe relative to the input signal TBX switches over time equal to one of the frequency division stages 1–3. The instability of the delay relative to the signal strobe at the output of the gated frequency divider is also equal to (, since the division stage 4 is switched by the signal from the output of element 6. When the subsequent bins arrive, the divider works as before, at the time tio The gated frequency divider is set to the initial state. When the next strobe arrives at time tj, the gated frequency divider functions in the same way. Thus, at the output output frequency (divided) pulses are output with an instability of the output pulse delay relative to the strobe by. Equal of the invention A gated frequency divider containing m frequency division stages, the input of the first of which is connected to the input bus, and the control inputs and all frequency division cascades are connected to a gate signal bus, characterized in that, in order to reduce the instability of the output pulse delays relative to the gate, the delay block and the OR element, whose inputs are connected to the outputs of all frequency division stages except. the last, and the output is connected to the input of the last cascade of frequency division, the inputs of all stages of frequency division, except the first and last, are connected to the outputs of the delay unit, the input of which is connected to the input gateway. Sources of information taken into account during the examination 1. USSR author's certificate No. 445988, cl. H 03 K 23/02, 05.10.72.

2. Design of microelectronic digital devices. Ed. Mayorova S. A., 1977, p. 146.

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