SU913457A1 - Device for diagnosis of address circuits of rapid-access storage - Google Patents

Description

The invention relates to storage devices.

A device is known for diagnosing addressable RAM circuits, which contains an address counter, a cycle counter, implication elements, and an I £ 11 element.

A disadvantage of this device is that it does not provide localization of faults of address circuits of memory.

The closest technical solution to this invention is a device for diagnosing addressable memory circuits, comprising a test generator connected through an adapter to a monitored memory, a valve block connected in series, a register and a display unit, the address outputs of the test generator connected to the inputs of the valve block, and the first and second control outputs respectively

with the register reset inputs and the control input of the valve block) 21.

The disadvantages of this device are low diagnostic accuracy and reliability of the device, since it does not determine the type of the detected malfunction and, moreover, reliable localization of faulty address circuits is possible only if there are no other faults in the monitored memory.

• The purpose of the invention is improving the diagnostic accuracy and reliability of the device.

This goal is achieved by the fact that the device for diagnosing the address circuits of the RAM contains a signal level matching unit, the first group of elements I, the first register, the first display unit and the test signal generator, the address outputs of which are connected to the inputs of the elements AND of the first group and the inputs of the first groups of 3

913457

four

Dov of the signal level matching unit, the inputs of the second group of inputs of which are connected to the informational outputs of the test signal generator, the first control output of which 5 is connected to the reset input of the first register, the inputs of which are connected to the outputs of the And elements of the first group, and the outputs to the inputs of the first display unit, the inputs of the third group of exo ^- 10 dov and one of the outputs of the signal level matching unit are the inputs and outputs of the device, respectively; an encoder, a decoder, and a group of programmable elements 15, NOT, are entered the detector, the comparison circuit, the second group of elements And, the second register and the second display unit, the inputs of the programmable elements of the NOT first group are connected to the outputs of the encoder, and the outputs to the inputs of the fourth group of inputs of the signal level matching unit, the other outputs of which are connected to the outputs of the programmable elements NOT 25 of the second group, the outputs of which are connected to the inputs of the detector and the decoder, the outputs of which are connected to one of the inputs of the comparison circuit, the other inputs of which are connected to the input of the encoder and the address the outputs of the test signal generator, the outputs of the comparison circuit are connected to the inputs of the elements of the second group, the outputs of which are connected to the inputs of the second ₃₅ register, whose outputs are connected to the inputs of the second display unit, and the reset input is connected to the first control output of the test signals generator, the second and third control outputs of which are connected respectively to the control inputs of programmable elements of NOT groups and to the synchronization input of the detector, the first and second outputs of which are connected ₄₅ to the control the inputs of the elements And, respectively, of the first and second groups.

Address

The drawing shows a functional diagram of the proposed device.

The device contains a generator of 1 test signals, block 2 matching the levels of signals. In addition, the monitored RAM 3 is depicted. The device also contains the first group of 4 elements AND, the first register 5, the first display unit 6, the encoder 7, the first 8 and the second 9 groups of programmable elements NOT, the decoder 10, the detector 11, the comparison circuit 12, the second a group of 13 elements And, the second register 14 and the second block 15 of the display. The number of bits in registers 5 and 14 corresponds to the number of address circuits.

R

The device works as follows.

The device operates in two modes: the mode of recording information by the addresses generated by generator 1, and in the mode of reading the recorded information, in which the fault is located the address circuits of the monitored memory 3. Both modes are repeated with inverted recorded data. The result of the localization of faults is indicated by the display units 6 and 15. In the recording mode, generator 1 generates a sequence of addresses, which is converted by the encoder 7 into a sequence of input data for recording in the monitored memory 3. "All codes of the recorded data, except for the last ^one , are the binary number containing the" O "of the corresponding digit addresses. The sequence of addresses and data, for example, for RAM 3 with a volume of four K words of eight digits is presented in the table:

Input data

00000000

1 1 'o

one

110 11

1111

0 0 1 0 0 0 0 1

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Address

111110 111111

1111110 11111

11111110 1111

111111110 111

1111111110 11

1 1 1 1 1 1 1 1 1 1 1 1

111111111110

1 1 1 1 1 1 1 1 1 1 1 1

In read mode, generator 1 generates the same address sequence as when writing, and provides for reading from the monitored memory 3 information recorded in it in write mode. Read information without changes is transmitted through block 2 and a group of 9 elements And to the inputs of the detector 11, which selects a code consisting only of units, and analyzes the readable information on the parity of the number of units. The decoder 10 converts the binary code of the first four bits of the output information into a decimal address code (according to the table), which is compared by comparison circuit 12 with the corresponding address code generated by generator 1. Comparison circuit 12 performs a bitwise comparison of incoming codes. Detection by the detector 11 of a code consisting only of units indicates the presence of a malfunction (constant "Ϊ" or "0") in the address chain. In this case, the detector 11 permits writing “1” to the discharge of register 5, corresponding to the current address containing the zero, and writing to register 14 is prohibited. When the detector detects a code 11 that contains an even number of units (different from the code consisting of all units), it allows writing “1” to the bits of register 14, corresponding to those bits of the codes compared by circuit 12, in which a discrepancy was detected. Register 14 fixes short-circuited address circuits .The blocks 6 and 15 of the display indicate the correspondingInput data

1 0 1 0 0 0 0 0

0 1 1 0 0 0 0 0

1 1 1 0 0 0 0 1

0 0 0 1 0 0 0 1

1 0 0 1 0 0 0 0

0 1 0 1 0 0 0 0

1 1 0 1 0 0 0 1

11111111

There are responsible address chains not moving in the constant state "0" or "1", and short-circuited chains.

When an odd number of units is detected, detector 1I prohibits writing to registers 5 and 14, excluding writing false information. Thus, the influence of other faults resulting in single errors in the read information is eliminated.

To obtain complete diagnostic information, the entire process is repeated with inverting the recorded information. At the same time, groups 8 and 9 of programmable elements N € are configured to invert information. This allows you to detect and localize all short-circuited address chains and all address chains that are in the constant "0" or

ι III

The time to diagnose address circuits is 4 (1 O ₂ N + 1) memory access cycles, where N is the number of words in the RAM 3 ·

The technical specifications of the proposed device are in its higher, in comparison with the known, accuracy of diagnostics of malfunctions and reliability.

Claims (1)

Claim A device for diagnosing addressable memory circuits, containing a signal level matching unit, the first group of elements AND, the first register, the first display unit and the test signal generator, ad7 ' 913457 ^! eight The main outputs of which are connected to the inputs of the AND elements of the first group and the inputs of the first group of inputs of the signal level matching unit, the inputs of the second group of inputs of which 5 are connected to the information outputs of the test signal generator, the first control output of which is connected to the reset input of the first register, whose inputs are connected to the outputs elements of the first group, and the outputs to the inputs of the first display unit, the inputs of the third group of inputs and one of the outputs of the signal level matching unit are respectively the 15th input device outputs, characterized in that, in order to improve the diagnostic accuracy and reliability of the device, it contains an encoder, a decoder, groups of programmed elements NOT, a detector, a comparison circuit, a second group of elements And, a second register and a second display unit The inputs of the programmable elements are NOT the first group are connected to the outputs of the encoder, and the outputs are the inputs of the fourth group of inputs of the signal level matching unit, the other outputs of which are connected to the inputs of the programmable elements NOT 30 the second group, the outputs of which are connected to the inputs of the detector and the decoder, the outputs of which are connected to one of the inputs of the comparison circuit, the other inputs of which are connected to the inputs of the encoder and the address outputs of the test signal generator, the outputs of the comparison circuit are connected to the inputs of the elements of the second group whose outputs are connected with the inputs of the second register, the outputs of which are connected to the inputs of the second display unit, and the reset input is connected ,, to the first control output of the test signal generator, the second and third control outputs The ports of which are connected respectively to the control inputs of the programmable elements of NOT groups and to the synchronization input of the detector, the first and second outputs of which are connected to the control inputs of the And elements of the first and second groups, respectively.