SU911615A1

SU911615A1 - Storage device

Info

Publication number: SU911615A1
Application number: SU792865405A
Authority: SU
Inventors: Евгений Михайлович Богданов
Original assignee: Предприятие П/Я В-8751
Priority date: 1979-12-26
Filing date: 1979-12-26
Publication date: 1982-03-07

Description

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Изобретение относитс к запоминающим устройствам и может быть использовано , в устройствах дл программируемых телеигр, а также в устройствах растровых дисплеев.The invention relates to memory devices and can be used in devices for programmable game shows, as well as in raster display devices.

Известное запоминающее устройство , используемое дл формировани растра и изображени на экране-телевизионного приемника, -содержит блок оперативной пам ти и,;;преобразователь цифровой инс1)ормации ,,3 видеоинформацию Ц. : , .The known storage device used to form a raster and image on the screen of a television receiver contains a memory block and, ;; a digital converter of information 1) information ,, 3 video information C.:.

Недостаток этого устройства состоит в том, что требуетс блок оперативной пам ти повышенного быстродействи .The disadvantage of this device is that a high-speed RAM is required.

Наиболее близким техническим решением к предлагаемому вл етс запоминающее устройство, содержащее блок оперативной пам ти, коммутаторы , логические элементы 2.The closest technical solution to the proposed is a memory device containing a block of RAM, switches, logic elements 2.

Недостатками этого устройства вл ютс невысокое быстродействие . и трудность его использовани безThe disadvantages of this device are low speed. and the difficulty of using it without

существенных переделок в качестве устройства дл программируемых телеигр . -. significant rework as a device for programmable TV games. -.

Цель изобретени - повышение быстродействи устройства. . Поставленна цель достигаетс тем, что в запоминающее устройство, со ,держащее блок оперативной пам ти, коммутатор, регистры и мультиплексор , причем адресные входы блока The purpose of the invention is to increase the speed of the device. . The goal is achieved by the fact that in a memory device, with, holding the RAM block, switch, registers and multiplexer, and the address inputs of the block

Claims

The 10 RAM is connected to the switch outputs, the register outputs are connected to the multiplexer information inputs, the output of which is the output of the device, the control inputs of the multiplexer, the registers and the switch are one of the inputs of the device, two are entered. groups of NAND elements and a decoder, one of the outputs of which are connected to the first inputs of the NAND elements of the first group, the second inputs of which are connected to the outputs of the main memory unit, and the outputs from the first inputs 39 of the NAND elements of the second group, Their inputs are connected to other outputs of the decoder as well. the outputs to the information inputs of the registers and the memory unit, the inputs of the decoder are other inputs of the device. The drawing shows a block diagram of the proposed device. The device contains a block of 1 memory, a decoder 2, the first 3 and second i groups of elements AND-NOT, registers 5 and 6, the switch 7 and the multiplexer 8.. The address inputs of unit 1 are connected to the outputs of switch J, the outputs of registers 5 and 6 are connected to the information inputs of multiplexer 8, the output of which is the output of the device, the control inputs of multiplexer 8, registers 5 and 6, and switch 7 are one of device inputs. One of the outputs of the decoder 2 is connected to the first inputs of the elements AND-NOT 3 whose second inputs are connected to the outputs of block 1, and the outputs to the first inputs of the elements AND-NOT k, the second inputs of which are connected to the other outputs of the decoder 2, and the outputs to information inputs of registers 5 and 6 and block 1, inputs of decoder 2 are other inputs of the device. The storage device operates as follows. The device receives electrical signals that characterize the location of each elementary point of the recorded image on the screen of a TV or video monitor (not shown). The location of this point is characterized by coordinates both on the line and on the frame. When recording the image on the field in increments, eight-way moves characterizing these coordinates are used. In the byte organization of the outputs of block 1, a decoder 2 is used with the organization of the fourth bit into sixteen outputs. It follows from the above that each point of the image is characterized by a code written and readable in block 1. To draw a symbol on the screen of a television receiver of any character, it is necessary to write a logical 1 or O for each of the addresses characterizing the shape and location54 of this symbol. For example, to record the coordinate codes characterizing a character, codes describing the shape of this character and its location on the screen are received from the arithmetic device of the game show. The first three bits of the code arrive at the decoder 2 and characterize the location of information 1 or O in the sector selected on the screen of the television receiver. The remaining (senior) bits through the switch 7 are fed to the address inputs of block 1. When there are corresponding signals that allow writing, the record occurs 0 | or 1 at the corresponding information input, which is specified by the first three bits. The change of the first bits of the code changes and the information input by which the next O or 1 is recorded. However, the information that has already been recorded. In block 1, it is not erased due to the trigger connection formed by two AND-NOT 3 and L elements and a memory cell. in recording mode. When reading the information codes from block 1, which are carried out by the signals of the clock game tele-generator. (not shown), the first three bits are sent to multiplexer 8, the rest through switch 7 to the address inputs of block 1, which determine where the information codes will be read. In order to remove the sampling delays of block 1, two registers 5 and 6 are used, into which the code from block 1 is written alternately. By means of multiplexer 8, this code is converted into a linear binary code, which is the carrier of the video information. In a game show, this linear code is added to the sync mixture to form a complete (or simplified) video signal. The level of logic O, for example, corresponds to the level of black, and the level of logical 1- corresponds to the level of white. Or vice versa, depending on the method of forming this video signal. The proposed device allows the recording of image elements capable of changing their position on the screen by a negligible amount (1-2 line increments) without shape distortions. The invention contains a memory device containing a block of RAM, a switch, registers and a multiplex, receiving the address inputs of the operative block 1 are connected to the outputs of the switch, the outputs registers are connected to the information inputs of the multiplexer, the output of which is the output of the device, control inputs of the multiplexer , egogistrov and. the switch is one of the inputs of the device, which is so that, in order to improve the speed of the device, it contains two g (AND-NOT elements and a decoder. 54 one of the outputs of which are connected to the first inputs of the NAND elements of the first group, the second inputs of which are connected to the outputs of the RAM block, and the outputs - with the first inputs of the elements of the NAND of the second group, the second inputs of which are connected to the other outputs of the decoder, and the outputs to the information inputs of the registers and the block RAM, entrances. Are other entries of the device.Sources of information taken into account in the examination 1. Funkschau fP 10, 1978, pp. 73.

2. For France, ff, cl. G 06 F 3/02, 1876 (prototype).