SU902070A1 - Reproducing unit for storage device - Google Patents

Description

one

The invention relates to computing and is intended for use in magnetic storage devices.

A reproducing unit for a memory device is known, comprising a buffer stage, a bridge circuit, a short-circuited delay line and a differential amplifier 1.

However, this block does not allow playback of read signals in the memory with a high degree of reliability, since it only introduces gating of read signals during their reproduction, which does not take into account the level of interference in the reading lines.

Closest to the proposed unit, containing in each bit nonlinear elements connected between the bit reading lines and the corresponding inputs of the reproduction amplifiers, the discriminator and the gating pulse shaper 2.

In this block, there are no elements and circuits that allow to take into account when playing the reading signal, the level of interference, which may vary due to various

causes from one read cycle to another.

The purpose of the invention is to increase the reliability of the memory.

The goal is achieved by the fact that

5 to a reproducing unit for a capturing device containing a first preamplifier of reproduction, the input of which is connected to one of the inputs of the block, a second preamplifier of reproduction, the input of which is connected to another input of the block, a discriminator and a gating driver, the outputs of which are connected to the corresponding inputs of the reproduction amplifier , two inverters, two adders, and deli 5 tel voltage are input, the input of which is connected to the output of the second preamplifier the output, the gate driver input and the input of the first adder, the second input of which is connected

20 to the output of the first inverter, and the output to the input of the second inverter, the output of which is connected to the first input of the second adder, the second input of which is connected to the input of the first inverter and the output of the first

the preamplifier is played, the output of the second adder is connected to the playback amplifier, and the output of the voltage divider is connected to the input of the discriminator.

The drawing shows a diagram of a playback unit for a storage device.

The playback unit for the memory device contains the first preamplifier 1 playback, the input of which is connected to one of the inputs 2 of the block. The second preamplifier 3 playback is connected to another input 4 of the block. The output of the preamplifier 3 playback is connected to the input of the voltage divider 5 and the first input of the first adder 6, the second input of which is connected to the output of the first inverter 1. The input of the first inverter 7 is connected to the output of the first preamplifier 1 playback and the input of the second adder 8, the second input connected to the output of the inverter 9, the input of which is connected to the output of the adder 6. The output of the second adder 8 is connected to the input of the playback amplifier 10, the second and third inputs of which are connected to the output of the forms The gateway 11 gates pulses and the output of the discriminator 12, the input of which is connected to the output of the voltage divider 5, and the input of the gate generator 11 of the gating pulses is connected to the first input of the adder 6.

When reading, the read signal together with the noise is fed to input 2 to preamplifier 1 of playback, from which output the amplified reading signal is fed to the input of inverter 7 and the first input of the second adder 8. At the same time, the second signal 4 is fed to the second input 4 second preamplifier 3 playback. After amplification, this signal is applied to the gate driver 11, the gating pulses, voltage divider 5 and the input of the first adder 6, to the second input of which an amplified signal of reading reverse polarity arrives. After adding these signals at the output of the adder 6, the voltage pulse corresponds to "O taking into account the presence of interference at the first input 2 of the block. This voltage pulse is applied to the input of the second inverter 9, and then to the second input of the second adder 8, the first input of which receives the amplified reading signal. Thus, at the output of the adder 8, a signal is formed that corresponds to the voltage amplitude of the information signal, which is fed to the vhrd reproduction amplifier 10, to the second input of which a strobe pulse is applied from the gate generator 11. To the third input of the playback amplifier 10, a discrimination level is supplied from the output of the discriminator 12, which is generated by the magnitude of the reference signal using a voltage divider 5. When reading the information "O, the second input of the adder 8 is amplified: a negative reverse polarity reference signal with noise, which is also fed to the input of the adder 8. Therefore, the output of the adder 8 produces a signal proportional to the reverse polarity of the reference signal. This signal is not amplified at reproduction amplifier 10, as it does not exceed the level of discrimination. The use of two inverters, two adders, and a voltage divider increases the reliability of the unit, and thus the efficiency of using the memory in which it is used.

Claims (2)

1. USSR author's certificate No. 410454, cl. G 11 C 7/02, 1974. 2. USSR author's certificate No. 448479, -kl. G 11 C 7/00, 1974 (prototype).