SU894737A1 - Device for reproducing variable-in-time coefficients - Google Patents

Description

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The invention relates to automation and computer technology and can be used in specialized automation devices and as part of hybrid computing systems.

A device for simultaneous reproduction of several time-varying voltages is known, comprising a pulse generator, a control unit, a controlled frequency amplifier, a counter, a memory unit, digital-to-analog converters, an inverter, an adder, a switch and a multi-channel storage unit}.

The drawback of the device is its limited scope, since it does not allow the creation of the product of independent variables and time-varying voltages.

It is also known a device for reproducing time-varying coefficients, comprising a pulse generator, a shift register 2.

hectare, counter, decoder, function switching unit, memory block, switching unit, sign trigger, reversible counter, and output and digital-analog duplication unit.

This device has high performance due to the almost instantaneous switching of the type of coefficients reproduced in time, but it has a limited area of application, since it does not allow the simultaneous reproduction of several time-variable coefficients.

The closest to the present invention is a device for reproducing variable time coefficients, comprising a pulse generator connected by an output to the first input of the main element AND and a counting input of the first counter connected by a higher bit output to the counting input of a second counter, the subclamp outputs of the first the group of inputs of the first decoder connected by the output to the input of the 5th block of memory connected by the sign output to the input of the sign trigger, and the digital outputs to the first group of inputs n The code-frequency eductor connected by the second group of inputs to the bits of the first sweeper’s bits and the output to the second input of the main element I connected to the counting input of a reversible counter connected by the control input of the reverse with the output of the character trigger, and the bits output the information inputs of the main register connected by the outputs to the digital inputs of the main digital-analogue duplicating unit, the analog input of which is the first input of the device, and the output through the main operational the amplifier is connected to the first output of the device, the outputs of the bits of the first and second counters are connected to the first group of inputs of the code comparison unit connected by the output to the control input of the main register, and the second group of inputs to the outputs of the analog-digital converter connected to the bus input sweep signal 3.

A disadvantage of the known device is the limited field of application, since it allows you to simultaneously reproduce only one time factor.

The purpose of the invention is to expand the field of application of the device by simultaneously reproducing several time variable coefficients.

The goal is achieved by the fact that a device for reproducing time-varying coefficients, comprising a pulse generator connected by an output to the first input of the main element AND and a counting input of a first counter connected by a higher bit output to a counting input of a second counter connected by bits output to the first group the inputs of the first decoder connected by the outputs to the inputs of the memory unit connected by the sign output to the input of the character trigger, and the digital outputs to the first group of inputs A code-frequency divider connected by a second group of inputs to the bits of the first counter, and an output to the second input of the main element I connected to the counter input of a reversible counter connected to the reverse control input with a sign trigger output, and the bit outputs to informational the inputs of the main register connected by the outputs to the digital inputs of the main digital-analogue duplicating unit, the analog input of which is the first input

devices, and the output through the main operational amplifier is connected to the first output of the device, the outputs of the bits of the first and second counters are connected to the first group of inputs of the code comparison block, nt-1 elements AND are additionally introduced (where n is the number of simultaneously playing time variables) , n-1 registers, n-1 digital analogue multiplying blocks, n-1 operational amplifiers, delay element, second decoder; the third counter and modulo p counter connected to the bit outputs from the second group of inputs of the first decoder and the inputs of the second decoder, each first () output of which is connected to the first input of the i-ro additional element And connected by the second input to the output of the block of the comparable codes connected by a second group of inputs to the outputs of the bits of the third counter connected by a counting input to the output of the most significant bit of the counter modulo n connected by a counting input to the output of the older bit of the second counter, inverse output The bits of the first and second counters are connected to the inputs (p + O of the additional element I connected by the output to the additional input of the first decoder and the input of the delay element connected by the output to the input of the control for setting the code of the reversing estimator

S of which are connected to the digital outputs of the memory unit, and the outputs of the bits to the information inputs of the additional registers, the i-th () additional register connected to the control input with the output () -ro of the additional element I, and the outputs with digital inputs An additional digital-to-analog multiplying unit, the analog input of which is the) input of the device, and the output through the i-th additional operational amplifier is connected to the (+1) output of the device.

Moreover, the control input of the main register is connected to the output of the first additional element I.

The drawing shows a block diagram of a device for reproducing time-varying coefficients.

The device contains a pulse generator 1 connected by an output to the first input of the main element AND 2 and the counting input of the first meter 3. connected by the high-order output to the counting input of the second counter 4. The counter t is connected by bit outputs to the first group of inputs of the first decoder S connected by the outputs with inputs of memory block 6. Memory block 6 is connected by a sign output to the trigger input of 7 characters, and digital outputs are connected to the first group of inputs of the code-frequency converter 8. Converter 8 is connected to the second group of inputs with outputs of counter 3 bits and with output to the second input of element 2. Element And 2 is connected by output to counting input of reversible counter 9 whose reverse control input is connected to the output of trigger 7 of the digit and the output of bits with the information inputs of the main register 10. The register 10 is connected to the outputs by qi (the inputs of the main digital-to-analog duplicating unit 11, the analog input of which is the first input of the device and the output through the main operational amplifier 12) It is connected to the first output of the device. The bits of counters 3 and 4 are connected to the first group of inputs of the code comparison unit 13. Counter H modulo n (where n is the number of simultaneously variable time coefficients) connected to the outputs of the bits with the second group of inputs of the decoder 5 and the inputs of the second decoder 15- Each (liUn) output of the decoder 15 is connected to the first input of the i-th additional element AND 1ft connected by the second input to the output of the code comparison unit 13. Unit 13 is connected by a second group of inputs to the outputs of the bits of the third counter 17 connected by a counting input with an output of the most significant bit of counter k modulo p. Counter 1 is connected by a counting input to the output of the most significant bit of counter i. InBepCHule outputs bits of the counters 3 and k are connected to the inputs (P4-1) of the additional element And 18 connected to the auxiliary input of the decoder 5 and the input of the delay element 19. The output of the delay element 19 is connected to the control input of the installation of the reversible counter code 9 whose installation inputs are connected to the digital outputs of memory block 6, and the outputs of the bits to the information inputs of the additional register OBOB 20. Each i-th () register 20 is connected by a control input with the output of the (5 + 1) -th element AND 16, and the outputs with the digital inputs of the {-th additional digital-analogue multiplying unit 21, the analog input, which is the (5 + 1) -th input of the device, and the output via the i-th additional operational amplifier 22 connect ene with a (4-1) th output of the apparatus. The control input of the register | 10 is connected to the output of the first element And 16.

The device works as follows.

Required variables in time t

the coefficients f, - (t) (where) are implemented in the device by the piecewise linear approximation method with a uniform arrangement of the nodes of the approximating functions along the axis of the argument t. The initial value of each of the approximating functions, corresponding to the first approximation node, is specified directly by the ordinate value, and all subsequent nodes are increment values of ordinates and increment signs of the approximating functions on the corresponding approximation parts. Presented in this way

The information on the value of the ordinates of the approximating functions in the nodes of the approximation is encoded with a binary code and entered into the memory block 6.

The time t in the device is counted by the third counter 17, KO-t that together with the first and second counters 3 connected in series and the counter 1 modulo n

recalculate the square pulses from the output of the generator 1. During the time corresponding to the overflow period of the counter H modulo n, when the state of the counter 17 remains unchanged, the device alternates the time sweep of all n approximating functions, the current values of the ordinates of which are ultimately formed reversible counter 9. The OUTPUT state of counter 17 modulo n determines the sequence number of raevertor weems functions, and the state of counter outputs k is the sequence HOf4ep of the current section eynoy of approximation. The output signals of these counters provide via the decoder 5. a selection of the current values of the increments of the ordinates of the nodes of the approximation of the deployed function from the 6 block of memory, the binary code of which is fed to the first group of inputs of the code-frequency converter 8. Converter 8, controlled by the second group of inputs by counter 3 | generates at the output a counting resolution signal, which is fed to the second input element I 2 and permits the passage of rectangular pulses of generator 1 to the counting vshed of the reversible counter E, thereby obtaining the specified slope of each plot of approximation of the function being developed. The operation of the code-frequency converter 8 is described by a logical expression, .v n-i-Va VVVi-Va- -1. where is ftt code on the outputs of counter 3 bits; v.-v code on digital outputs of memory block 6} output signal of 8 code-frequency converter. This expression shows that the number of pulses arriving at the counting input of the reversible counter 9 at each section of the linear approximation clearly corresponds to the current value of the function increment code. The increment sign is taken into account by feeding the control of the reverse of the counter 9 through the trigger-7 sign to the input; signal from the sign output of the memory block 6. The selection of the initial values of the approximating functions from the memory block 6 and their recording into the reversible counter 9 from the setup inputs of the latter is carried out before starting the current function, i.e. at the point in time when counters 3 and i are in zero conditions. Decoding zero

the output states of the counters are produced with the help of (n + 1) -th additional element And 18, the inputs of which are connected to all the variable coefficients for the new value of the argument is repeated. to the inverse outputs of the bits of the counters 3 and, and the output to the additional input of the decoder S and through the delay element t9 to the input of the control of the installation of the reverse counter code 9- The delay element 19 provides for the delay in writing information into the reverse counter 9 for the time required for select from block 6 of memory. The signals from the outputs of the bits of the counters 3 and, as follows from the logic of the operation of the device, serve as the time argument t of each of the functions approximating the variable coefficients. Consequently, at the moments of time when the state of the outputs of these counters coincides with the state of the outputs of the counter 17 of the time argument t of variable coefficients, the current value of the ordinate of each 1st approximating function formed in the reverse with the receiver 9 is equal to the current value of the coefficient. The coincidence of the states of the outputs of the counters 3 and the states of the outputs of the counter 17 is fixed by the block 13 of the code comparison, the signal from the output of which goes to the second input of additional elements And 16. The decoder 15 decodes every 1st state of the counter I modulo pi, strobe 1- The second element AND 16 polls the output state of the code comparison block 13. The coincidence signal from the output of block 13. passes through the i-th element I 16 and is fed to the control input of the corresponding register 10 and 20 connected by information inputs to the outputs of the reversing counter 9 In this case, the value of the current ordinate of the approximating function is written to the selected i-th register (t), corresponding to the value of the variable coefficient f; (t). When the counter overflows, the modulo counter 14 goes to the (1 + 1) -th state corresponding to the sweep of the () -th approximating function, and at the time instant, the value f; i4-i will be written to the (1 + 1) -th register in the same time. (t) f. (t) and so on. After a full time (1 / 1I of counter I modulo n, counter 17 goes to the next state and process, as a result of which the values

Codes of the current values of each i-ro variable coefficient (t) are fed to the digital inputs of the corresponding digital-analogue multiplying blocks 10 and 21, the analog inputs of which receive input signals y. As a result, the voltage of the form is formed at the outputs of the device.

z i 1,2, .... p.

Thus, the proposed device, in comparison with the known, allows simultaneous reproduction of several time-variable coefficients, which expands the possible area of its application in specialized automation devices and in hybrid computing systems.

Claims (3)

Invention Formula A device for reproducing time-varying coefficients, comprising a pulse generator connected by an output to the first input of the main element —And to a counting input of a first counter connected by a higher bit output to a counting input of a second counter connected by the outputs of bits to the first group of inputs of the first decoder connected by outputs to the inputs of a memory unit connected by a sign output to the input of a sign trigger, and digital outputs to the first group of inputs of a code-frequency converter connected the second group of inputs with the outputs of the bits of the first counter, and the output with the second input of the main element AND connected to the counter input of the reversible counter connected to the input of the reverse control with the output of the sign trigger, and the outputs of the bits connected to the information inputs of the main register connected the outputs to the digital inputs of the main digital-analogue multiplying unit, the analog input of which is the first input of the device, and the output through the main operational amplifier is connected to the first output CTBA, and outputs the bits of the first and second counters are connected to inputs of the first group unit comparing the codes, characterized in that in order to use the field expansion device due to the simultaneous reproduction of several variables in time koef10 In addition, n + 1 elements I are entered into it (where n is the number of simultaneously reproduced variable in-time coefficients), J n-1 registers, n-1 operational s, multiplication blocks, n-1 operational amplifiers, element zader; the second decoder, the third counter and a modulo-n counter connected by the outputs of the series with the second group of inputs of the first decoder and the inputs of the second decoder, each () output of which is connected to the first input of the 1st additional element And connected by the second input with the release of the block cf The codes are connected by the second group of inputs to the outputs of the bits of the third counter connected by a counting input to an output of the highest bit 2Q of a counter modulo n connected by a counting input to the output of the senior bit of the second counter, and the inverse outputs of the bits of the first and second counters are connected to entrances 25 (n + 1) -th additional element And connected by the output to the additional input of the first decoder and the input of the delay element connected by the output to the control input of the set, which code of the reversible counter, the installation inputs of which are connected to the digital outputs of the memory unit, and the outputs of the bits to the information inputs of the additional registers, each i-th (1 1bp-1) additional register connected by a control input to the output {i-fl) -ro of the additional element And, and the outputs - to digital inputs i-ro additional digital tax multiplier  block. The analog input of which is the (1h-1) -th input of the device, and the output through the i-th additional operational amplifier is connected to the (i + l) th output of the device, and the control input of the main register is connected to the output of the first additional element . Sources of information taken into account in the examination 0 1. USSR author's certificate in application number 2832271 / 18-24, cl. G About G 7/26, 1979. 2. USSR Author's Certificate for Application No. 2723786/1 8-2i, 5 cl. G About G 7/26, 1979. 3. USSR author's certificate 10 of the application N 2706l55 / l8-2t, , cl. G About G 7/12, 1979 (prototype). f P Vis TG GT- -f s. Ilk II s I Ch F y 3 H fyl y SJJ :: J y, . .r-yff.d)  // I