SU875640A1 - Pulse counter - Google Patents

Description

(54) PULSE COUNTER

I

This invention relates to pulsed

technology and can be used in devices of automation and remote control for counting pulses, output the accumulated information and its storage during power interruptions.

A known electronic pulse counter with a periodic output of accumulated information by a serial binary code containing the actual counter, the triggers of which are connected via elements I to the installation inputs of 1 trigger shift register, the output of which is connected via an output driver to the output bus of the device, a pulse generator connected to the control circuit The outputs of which are connected to the second inputs of the elements I, the installation “About the counter and the input of the shift register, as well as to the inputs of the output form ovatel 1.

A disadvantage of the known counter is the loss of information during power interruptions.

The closest in technical essence to the invention is a pulse counter, which stores information during power interruptions, is built on the main storage device and contains

an input pulse bus, a pulse generator, a bit distributor connected via bit switches to numeric linear ferrite cores, the windings of which are connected to the output keys of the "1 and polling" keys and the input of the read amplifier, the output of which is connected to the input of the "1 trigger" switch, a reset signal shaper connected to the input of the installation “On the discharge distributor and the element 2”.

However, the pulse counter forms

10, the output signal when it overflows and does not allow outputting information about the number of accumulated pulses in the course of its operation, which limits its use.

The purpose of the invention is to enhance the functionality of the pulse counter.

This goal is achieved by the fact that a pulse counter containing an input pulse bus, a pulse generator, a separate distributor connected via a digital switch to a numerical line of ferrite cores, the windings of which are connected to the outputs of the write keys

"I and polling, and the input of the read amplifier, the output of which is connected to the installation input" 1 of the first trigger, a reset signal shaper connected to the input of the rectifier, "On the bit distributor, first element I," entered the pulse synchronizer, half adder, synchronizer pulse shaper, key write "Oh, the second trigger with a counting input, the second element And the output driver, and the pulse generator is connected to the input of the synchronization pulse shaper, the outputs of which are connected to the gating inputs of both elec And, a read amplifier, an output driver, an installation input “About the first trigger, inputs of a poll key and a bit distributor, the auxiliary output of which is connected to the input of the output shaper marker and the synchronization input of the pulse synchronizer, whose information input is connected to the bus of the input pulses, and the output connected to the installation input "1 second trigger, the output of which is connected to the first input of the half-adder and the second inputs of both elements And, the output of the first trigger is connected to the information in the output of the imaging unit and the second input of the half-adder, the overflow output of which through the first element AND and the write key "O is connected to the additional winding of the numerical scale, and the output of the sum is connected to the third input of the second element And, the output of which is connected to the input of the recording key" 1 and the counting input the second trigger, the installation input “About which is connected to the reset input of the synchronization of pulses and the output of the reset signal generator, in addition, the numeric Li-ik is performed on the cores with non-destructive reading of information.

The drawing shows a diagram of the pulse counter.

The device contains a key 1 poll, write keys "O 2 and" 1 3, numerical line 4, amplifier 5 readings, bit switches b, bit distributor 7, first and second elements And 8 and 9, generator 10 pulse: s, driver 11 synchronization pulses, half adder 12, the first trigger 13, the second trigger 14, the output driver 15, the synchronizer 16 pulses, the driver 17 of the reset signal and the bus 18 of the input pulses.

The device works as follows.

When the controller is switched on, the reset signal shaper 17 sets the discharge valve 7, the synchronizer 16 and the trigger 14 to the initial state.

The generator of 10 pulses periodically starts the shaper of 11 synchronization pulses, which in one cycle of operation produces one at each output

impulse of a certain duration, providing a temporary interaction of the counter elements. The first pulse of the former II sets the trigger 13 to the “O” state, the second triggers the interrogation key 1,

providing readout of information from the digit line 4, corresponding to the open bit key 6, while the read signal is amplified by the read amplifier 5, to the input of which gating a short third pulse is applied

 shaper 11, which increases the noise immunity of the read amplifier 5.

The output signal of the amplifier 5 sets the trigger 13 to the state "1 if" I was read from the numerical scale.

The fourth pulse of the imaging unit 11 is fed to the gating inputs of the elements 8 and 9 and determines the duration of the recording currents that are generated by the recording keys "O 2 or" 1 3 depending on the signals at the remaining inputs of the elements

U And 8 and 9.

The fifth pulse gates the output driver 15, the duration of the pulses of the output counter of the sequential code is determined.

The sixth pulse changes the state of the distributor 7, providing a reference to the next bit of the number bar 4.

During the pauses between the counting pulses, only the output of the read is made.

d from numerical liiyaki 4 information through amplifier 5, trigger 13 and output driver 15 to the counter output, and writing information to the numerical scale 4 is blocked by the signal “O from the direct output of trigger 14, which is fed to the inputs of the And 8 elements

S and 9.

The counting pulse from the bus 18 is fed to the synchronizer 16 pulses, which after polling the pulse from the auxiliary output of the bit distributor 7 produces a signal that sets the trigger 14 to the state "1." The output signal of the trigger 14 prepares the elements AND 8 and 9 for operation in the recording mode and feeds the first input of the half adder 12, to another input of which the output of the trigger 13 is received, the code read from the numeric line 4 information.

When reading "I from the low-order digit of the numeric ruler 4, the half-adder 12 at the overflow output generates the signal" 1 preparing element 9 for operation. Strobe pulse from the output of the imaging unit 11 through the element And 9 starts the recording key “O 2, which generates the recording current; the first decimal place of the first digit of the number bar 4 to the state "O. The entry "O to the remaining bits of the numerical line 4 continues until the reading" O of any digit of the numerical line 4,

then, at the output of the sum of the adder 12, a signal "1" is generated, which prepares the element AND 8 for operation.

Then, the strobe pulse from the output of the imaging unit 11, through the element And 8, starts the recording key “I and, cut off the output pulse, switches the trigger 14 to the state“ O. The “I” key will generate a signal that sets the digit of the numeric scale 4, from which “0” was read to state “1, and the output signal“ 0 from trigger 14 blocks AND 8 and 9, thereby prohibiting further recording of information in numeric line 4 until the next counting pulse arrives at the counter input.

When the power is interrupted, the output signal of the reset signal generator 17 sets the discharge valve 7 to the initial state, providing the beginning of the interrogation of information from the low-order bit, as well as the synchronizer 16 and the second trigger 14, which provides a pin from the false information recording in case of spontaneous installation of these circuits in the "1 with the restoration of power. ,

The use of newly introduced elements — a write key “O”, a sync pulse generator, a half adder, a trigger with a counting input, a pulse synchronizer and an output driver, as well as a numerical ruler on ferrite cores with non-destructive reading of information make it possible to organize periodic output of information from the counter and expands its use, for example, in telemetry systems with periodic information output. In addition, the introduction of a synchronization pulse shaper allows one to obtain optimal parameters for the operation of a numerical scale in the modes of recording and reading information.

Claims (2)

Invention Formula . A pulse counter containing an input pulse bus, a pulse generator, a bit distributor connected via bit switches to a numerical line of ferrite cores, the windings of which are connected to the outputs of the write keys 1 and the input amplifier of the read amplifier whose output is connected to the input of the device The first-flip-flop I, a reset signal shaper connected to the installation of an O bit distributor and the first AND element, characterized in that, in order to expand its functional capabilities, pulse chronizer, half adder, driver 0 sync pulses, write key "O, second trigger with counting input, second AND element and output driver, moreover, the pulse generator is connected to the input of the synchronization pulse generator, the outputs of which are connected to the input inputs of both AND elements, reading amplifier, output shaper, input the installation “On the first trigger, inputs of the interrogation key and the discharge distributor, the auxiliary output of which is connected to the input of the output driver marker and the synchronization input of the pulse synchronizer , whose information input is connected to the input pulse bus, and the output is connected to the setup input “1 of the second trigger, the output of which 5 is connected to the first input of the half adder and the second inputs of both elements And, the output of the first trigger is connected to the information input of the output driver and the second input of the half accumulator, the overflow output of which through the first element And the record key Q is connected to the additional winding of the numerical line, and the output of the sum connected to the third input of the second element I, the output of which is connected to the input of the write key “I and the counting input, the house of the second trigger, the input of the installation“ About which is connected to the reset input of the pulse synchronizer and course of the reset signal shaper. 2. A counter according to claim 1, characterized in that the number plate is made on cores with non-destructive reading of information. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 658744, cl. H 03 K 23/02, 1977.  2. USSR author's certificate No. 453805, cl. H 03 K 23/10, 1973 (prototype).