SU864235A1 - Multichannel meter of time intervals - Google Patents

Description

(54) MULTI-CHANNEL MEASURING TEMPORARY

INTERVALS

The invention relates to a measuring technique and can be used in systems for automatically measuring time intervals, in particular, for measuring the parameters of a watch movement. Known time interval meters are those containing a clock pulse generator, drivers, and counters l |. Closest to the invention is a multichannel meter containing coincidence circuits, a generator, a counter, reception triggers and a signal storage trigger, an address encoder, an OR 2 circuit assembly. A disadvantage of the known device is the low measurement accuracy. The purpose of the invention is to improve the measurement accuracy. This goal is achieved by the fact that a multichannel time interval meter containing coincidence schemes, a generator, a counter, receive signals and memory triggers, an address encoder, an OR circuit assembly, input signal conditioners, counters, blocks of address input keys and the first code input. And the second counters of the circuit And rewrite, And reset, block in Baud in the computer, circuit And continue polling, key start polling, circuit And prohibit polling, trigger polling, assembly circuits OR prohibit polling, circuit And start polling, block diagrams OR input, trigger p Sign, rewriting permission and scheme, reset permission and scheme, poll interrogation trigger, rewriting enable trigger, reset enable trigger, poll counter, polling circuit, Address-Time driver, Time driver, each of the device inputs n connected via a signal driver with one input of the receive trigger connected to the second input of the AND rewrite circuit, output connected to the first input of the trigger of its 3 channel memory, the second input of each of which is connected to the fault inputs of the first and the first output of each memory trigger is connected respectively to the first input of the matching circuit of its channel and through the AND reset circuit of this channel to the second input of the reception trigger signal of its channel the second output of the memory trigger of each channel connected to the input of the AND polling circuit of its own channel, the first inputs of the coincidence circuit and the AND polling circuit of the first channel are connected via the AND interrogation circuit with the output of the polling start key and the first And the first inputs of the match circuit and the AND poll pattern of all channels, and the first inputs of the match circuit and the AND poll pattern of the remaining (n-1) channels are connected to the output of the And poll circuit and the first input of the previous poll trigger , the second input of each of which is connected to the output of the matching circuit of its channel, the input of the address decoder and one input of the assembly of the ICH circuits, and the single outputs of the polling triggers of each channel are connected to the second # 1 inputs of the AND circuits of the corresponding channel a and with the P inputs of the circuit OR of the interrogation interrogation, the output of which is connected to the second input of the interrogation AND interdiction circuit, the output of the interrogation circuit AND of the corresponding channel is connected to the memory trigger trigger input and the second input of the interrogation circuit of this channel, the output of the generator having Start input, connected to the inputs of the overwrite enable trigger, poll counter, AND overwrite permission, and poll enable circuits, the second inputs of each of the last two are connected to one of the two overwrite enable trigger outputs, the second input of which is connected to the output of the interrogation counter and the output of the reset permit trigger, the output to which is connected to its second input and through the reset enable circuit AND. the second inputs of the AND reset circuits, and the output of the polling resolution AND enable is connected to the second input of the AND resolution reset and one input of the polling start key, the output of which is connected to one input and the interrogation prohibition, and the output of the overwrite resolution AND is connected to the first inputs AND rewrite each channel and with the input of the first counter, one output of which through the first block of input keys of the first counter is connected to one input of the OR input block, and the second output through the second counter and second block of code input of the second counter - from watts eye input block of input circuits and with the first input of the trigger of the sign, & f the stroke of which is connected to one input of the AND start polling circuit, one input of time and address formers, the last output of the circuit is connected to the second input of the key block input address block input key of the first counter and shaper Time, the output of which is connected to the second inputs of the trigger sign of the second block of keys to enter the code of the second counter and the third input of the circuit And the start of the poll, the output connected to the BTOpbW input of the key of the beginning of the poll, and One of the keys of the input address key is connected to the third input of the block of OR circuits, the output of which is connected to the input block in the computer. The drawing shows a block diagram of a multi-channel time interval meter. The multichannel time interval meter contains generator 1, first counter 2, second counter 3, memory triggers 4, rewrite enablement scheme 5, 1without resolution enable trigger 6, polling counter 7, interrogation permission AND scheme 8, reset enable trigger 9, reset permission And scheme 10, AND reset circuit 11, interrogation start key 12, interrogation AND continue polling 13, interrogation AND interdiction circuit 14, assembly of interrogation circuits OR interrogation interrogation 15, coincidence circuits 16, AND interrogation circuits 17, And rewriting 18, signal reception triggers 19, drivers signals 20, polling triggers 21 , address encoder 22, assembly of schemes OR 23, Address-Time 24 shaper, Time 25 shaper, AND polling beginning circuit 26, address input key block 27, code block 28 key entry block of the first counter, indication trigger 29, key code entry block 30 second counters

block diagrams OR input 31, input unit in the computer 32.

The first input of the generator I is connected to the Start bus, its second input is connected to the bus. Reset the reset inputs of the first 2, second 3 counters, the third inputs of the 19-signal trigger and the second inputs of the memory triggers 4, and the output is connected to the first input of the overwrite resolution And 5, the inputs of the rewrite enable trigger 6, the polling counter 7 and the first input of the polling AND resolution circuit 8. The first output of the rewrite permission trigger 6 is connected to the second input of the AND rewrite permission circuit 5, the second to the second input of the AND polling permission circuit 8, and the reset input is connected with the output of the poll counter 7 and the reset input of the reset enable trigger 9. The reset enable trigger input 9 is connected to the output of the reset enable resolution AND 10 and the first inputs of the reset AND circuit 11, and the output reset 10, the second input of which is connected to the output of the polling permission AND circuit 8 and the first input of the polling start key 12. The output of the polling originating key 12 is connected to the first inputs of the polling AND continuation circuit 13 and the first input of the polling inhibit And circuit 1A, the second input of which is connected exit build and OR schemes ban polling15. The first outputs of the memory triggers 4 are connected to the second inputs of the matching circuit 16 and the reset circuit 11, the second are connected to the second inputs of the polling AND circuit 17, and the inputs to the outputs of the overwriting circuit 18, the first inputs of which are connected to the outputs of the trigger 19, and the second with the output of the rewrite resolution AND circuit 5 and the input of the first counter 2. The inputs of the signal receiving triggers 19 are connected to the outputs of the second formers 20, and the fault inputs are connected to the outputs of the AND reset circuits 11. The second reset inputs of the memory trigger 4 are connected to the outputs AND circuits 13, continuing the polling and third inputs and polling I7. The second inputs of the circuits And the continuation of the poll 13 are connected to the outputs of the trigger of the poll 21 and the inputs of the assembly of the schemes of the IPD of the prohibition of the survey 15. The first inputs of the circuit: And match 16 and poll 17 except for the first

channel connected to the outputs of the circuits And the poll 17 and the first inputs of the trigger sign of the survey 21 of the previous channel. The first inputs of the matching circuit 16 and AND polling 17 of the first channel are connected to the output of the interrogation circuit AND AND 14. The outputs of the matching circuit 16, except for the last channel, are connected to the input w of the address encoder 22 and the circuit assembly OR 23. The output of the latter is connected to the first input of the imager Address -Time 24, the output of which is associated with the first input of the former Time 25, the first input

cxehod And the start of the survey 26 and the first inputs of the keys to enter the address 27 and enter the code 28 of the first counter, and the second input with the output of the trigger sign 29 and the second input of the circuit And the start of the survey

26. The output of the latter is connected to the second input of the polling start key 12, and the third input is connected to the output of Timer 25, the reset input of the rewriting trigger 29 and the first input of the key block 30 of the second counter. The outputs of the address encoder 22, the first 2 and second 3 counters are connected via the key blocks for the input of the address 27, code 28 of the first

counter, code 30 of the second counter with a block of circuits OR input 31, the outputs of which are connected to the inputs of the input block in the computer 32.

Before the start of measurement, the counters 2 and 3, triggers 4 and 19 are reset, and the generator 1 is started with the Reset and Start signals. The sequence of pulses produced by the generator 1 is fed to the input of the AND resolution overwrite 5, the trigger for overwriting resolution 6, the AND resolution of polling 8 and the poll counter 7. During the measurement, the sequence of pulses of the input signals is fed to the input of the signal generator 20 and written to trigger triggers (signal 19.

Claims (2)

The rewrite AND resolution scheme 5, interrogation AND resolution scheme 8, reset resolution AND scheme 10, rewrite resolution trigger 6, reset 9 and polling counter 7, the entire sequence of pulses produced by generator 1, is divided into a series of pulses. The number of pulses in a series is determined by the counter capacity of the polling 7. The division of the pulses into series is done in order to regulate the duration of the channel survey cycle. In this case, the cycle duration, equal to the series duration, is determined based on the required resolution of the meter. The first impulse from the generator I is supplied to the rewrite resolution AND scheme 5, the rewrite resolution trigger 6, the polling resolution AND scheme 8 and the poll counter 7. The rewrite permission trigger 6 prohibits the passage of this pulse through the polling permission AND scheme 8 Non-rewriting 5. Thus, the first pulse from the series is selected, which is fed to the second inputs of the AND-rewriting circuit 18, thereby ensuring the rewriting of signals to memory triggers 4 and the unit drift to the first counter 2. the volume of the same pulse is transferred to the overwrite resolution trigger 6, which prohibits the arrival of pulses through the rewriting circuit within the given pulse train and allows the arrival of pulses through the AND resolution of the poll 8 through the poll circuit. The second pulse passes through the AND resolution of the poll 8 and enters the AND circuit reset permission 10. The reset enable trigger 9 permits the arrival of pulses at the first inputs of the resetting circuits AND 11. The triggers memorize the 4 in which the signals were overwritten, give permission for the second input of the circuits and reset 11 and thereby quenching secu chat respective trigger receiving signals 19 and their reception prepara t sleduyushzih pulses. In addition, the second pulse through the key of the start of the poll 12 and the interrogation inhibit circuit 14 is fed to the coincidence circuit 16 and the AND circuit 17 of the first channel. If there is no signal on this channel, the memory trigger 4, reset by the Reset signal, allows the pulse to pass through the AND poll 17, and the pulse arrives at the 16 and AND 17 scan of the second channel. Such a process occurs until the channel through which the signal is received is detected. In this case, the memory trigger 4 prohibits the polling pulse from passing through the AND circuit 17 and enables the matching circuit 16. The pulse from the output of the matching circuit 16 goes to the input the encoder 22 and the assembly of the OR 23 circuits. With this, the address of the polled channel appears at the output of the encoder 22, and the output of the assembly of the OR circuits 23 is the signal that launches the Address-Time shaper 24. The pulse generated by the Address-Shaper 24, opens up inputting the code of the first counter 2 and the address code 27, and thereby providing through the block of circuits OR 31 and the block of input to the computer 32 a transmission to the computer of the address code and the signal arrival time. The same impulse is carried out by the forg "Time Tracker" in the event that the first counter overflows. In this case, the Time Shaper provides the formation of a pulse, which opens the input keys of the second c-code code, and after the information containing the channel address code and the time code, information about the state code of the second counter is entered. During the entire time when the information is entered into the computer by the circuit AND of polling 26, it is prohibited to receive any pulses through the key of the beginning of the polling 12, which eliminates the possibility of failure and increases the noise immunity of the circuit. The back edge of the pulse from the coincidence circuit 16 is thrown by a polling request poller 21, which prevents the polling pulses through the AND interdiction circuit 14 from assembling the circuits OR interrogating interrogation 15 and gives permission to the second input of the And propagation polling circuit 13 of the channel just polled. After the information about the polled channel is entered into the computer, the And polling start circuit 26 allows the polling pulses to pass through the polling start key 12. The next polling pulse that has passed through the polling start key 12 will not go back to the 16 and And continue polling schemes 17 of the first channel, since the assembly of the schemes OR 15 prohibits its passage through the interdiction interdiction 14, and will go to the first inputs of the diagrams AND continue the interrogation. Since in this case the resolution at the second input is present only for the scheme And the continuation of the poll 13, the channel of which is already simplified, then the pulse passed this circuit will reset the memory trigger just polled and interrogate the next channel through the AND poll 17 scheme the polling trigger 21 returns to its original state. All other channels are interrogated in a similar way. At the end of the polling cycle, the polling counter 7 is reset to zero and generates a pulse at the input, which is reset from the overwriting resolution triggers 6 and the reset resolution 9. The circuit returns the initial state and a new channel polling cycle begins. , Time intervals are measured in the following way. The signal received by the meter input is assigned the state code of counters 2 and 3 and the address 22 is formed by the encryption address of the channel through which the signal goes off. The state code of counters 2 and 3 is generated by binary 1 in 1 pulse counters, which are continuously received pulses with a period repetition equal to the duration of the measurement time Tc. Signals received during the TC are considered received at the same time, so the signals can be stored for some time in the triggers, which eliminates the possibility of failure. More than the cycle length measured. Invention Multi-channel time interval meter containing coincidence circuits, generator, counter, reception triggers and signal memory triggers, address encoder, OR circuit assembly, differing from the fact that, in order to improve measurement accuracy, drivers are introduced signals, counter, key blocks, input of the address and code entry of the first and second counters, schemes And rewrites, schemes AND reset, input block in the computer, scheme) And continue polling, key started polling scheme And interrogating the interrogation, triggers polling sa circuit assembly OR interrogation interdiction, interrogation AND start, block OR input circuit, feature trigger, rewrite enable AND schema, reset allow I. scheme, interrogate AND schema, rewrite enable trigger, reset enable trigger. polling counter, AND polling scheme, Address-Time driver, Time driver, with each of the device's p-inputs connected via a signal driver to one input of a receive trigger connected by an output to a second input of a re-write circuit, an output connected to the first input of a memory trigger channel, the second input of each of them is connected to the fault inputs of the first and second counters, the fault input of each trigger receiving signal and the fault input of the generator, and the first output of each trigger memory Connected respectively with the first input of the matching circuit of its channel and through the circuit AND reset of this channel with the second input of the trigger receiving signal of its channel, the second output of the memory trigger of each channel is connected to the input and polling of its channel, the first inputs of the matching circuit and the And poll circuit of the first channel are connected through the circuit And the interrogation prohibition with the output of the polling start key and the first inputs of the circuits And continue polling of all channels, and the first inputs of the matching circuit and the circuit And polling the remaining 1p- |) channels, CQ are connected to the output of the circuits Both the poll and the first input of the poll trigger of the previous channel, the second input of each of which is connected to the output of the matching circuit of its channel, the input of the address encoder and one input of the collection of OR circuits, and the single outputs of the t-pollers of each channel connected to the second inputs of the AND continuation circuits interrogation of the corresponding channel and with the p-inputs of the assembly of the CM schemes of the interrogation ban, the output of which is connected to the second input of the AND AND interrogation circuit, and the output of the AND circuit of the further polling of the corresponding channel is connected to the reset input trigger and storing the second input of the AND polling circuit of this channel, the output of the generator having the Start input, is connected to the inputs of the rewrite enable trigger, poll counter, AND rewrite permission, and the polling resolution circuit, the second inputs of each of the last two are connected to one of the two outputs overwrite trigger, the second input of which is connected to the counter output interrogation and output of the reset permit trigger, the output of which through the reset resolution AND circuit is connected to its second input and second inputs of the AND circuit, and the output of the polling resolution I circuit is connected to the second input of the reset resolution AND circuit and one input of the polling start key, w (stroke which connects with one input cue number, 1 and the interrogation ban, and the output of the AND resolution overwrite is connected to the first inputs of the AND rewrite schemes of each channel and to the input of the first counter, one output of which through the nepBbiii block of keys for entering the code of the first counter of the connection not with one input of a block of OR input circuits, and a second output through a second counter and a second block of keys for entering the code of a second counter with a second input of a block of UCHI input circuits and with the first input of a trigger of a sign, the output of which is connected to one input of the AND start polling circuit, one the entrances of the fopes of the time and address drivers are time, the output of the latter is connected to the second input and the start of the polling of the key block for the address input, the key block for entering the first counter code and the time generator, the output of which is connected to the second inputs of the trigger of the sign, the second key block for the second counter code and the third input of the circuit And the start of the survey, the output of the coynea with the second input of the key of the beginning of the survey, and the output of the key block of the address input is connected to the third input of the block of the OR input circuit, the output of which is connected to the input block of the computer. Sources of information taken into account in the examination I. „USSR author's certificate 530311 cl. G 04 F 10/04, 1974 (prototype), 2. USSR author's certificate No. 545967, class 04 F 10/00, 1975.