SU1499388A1 - Arrangement for transmitting messages in adaptive telemetery systems - Google Patents

Abstract

The invention relates to information and measurement technology and can be used in adaptive-address telemetry systems. The purpose of the invention is to increase the reliability of transmitted messages and simplify the device. The device contains a chronizer 1, an address code 2 and an information code 3, an information redundancy reduction block 4, a message code generator 5, a time interval coding block 6 consisting of binary counters 7.8, elements OR 9.13, trigger 10, elements AND 11.12. 1 hp f-ly, 2 ill.

Description

i

(L

 co co oo

100 iOO

i

Phage.1

31499

The invention relates to an information-measuring technique and can be used in adaptive-address telemetry systems.

The purpose of the invention is to increase the reliability of messages and simplify the device.

FIG. 1 shows a block diagram of a device for transmitting a message in adaptive telemetry systems j in FIG. 2 - f, the binary counter scheme is used.

The device (FIG. 1) contains a chronizer, address encoder 2, information encoder 3, information redundancy reduction unit 4, message code generator 5, time interval encoding unit 6 containing the first 7 and second 8 binary counters, the first element OR 9, trigger 10, first. 11 and second 12 elements and the second element OR 13.

The binary counter (FIG; 2) contains a register 14, a group of 15 elements AND 16, a pulse generator 17, an IDN element 18, a second register 19, elements 20 and 21, a trigger, 22, a pulse frequency divider 23, an element 24, a trigger 25, element 26, trigger 27, decoder 28,

The device works as follows.

Chronizer 1 delivers clock control pulses to the inputs of encoders 2 and 3 and -block 6 and counting pulses to the inputs of counters 7 and 8 of the block 6 for encoding time intervals. The information redundancy block 4 impulses at the moments of occurrence of significant samples to the trigger 10 input and pulses at the moments coinciding with the clock pulses applied to the input of block 4 from the chroniser 1, in the presence of a 24-hour count in block-4, to the inputs of the encoder 2 the addresses and elements are 11 and 12, and the countable essential readings are the input to the encoder 3 information. Using these pulses and samples, the encoder 2. addresses generates code combinations that display the channel number (the address of the parameter being measured) to which the reference belongs, encoder 3 generates a code that reflects the value of the essential reference of the parameter being measured, block 7 measures the intervals time between the true moments of the occurrence of significant samples and

forms corresponding time intervals-code combinations.

Code combinations from coder 2 outputs. 3 and block 6 are fed to the imaging unit 5, which forms the complete code of the message (reference). In the event that the time interval between the significant readings performed by block 4 exceeds the limits of unambiguous measurement of intervals (before the overflow of counters 7 and 8) by block 6, the latter generates a pulse to stop measuring the interval of time (pulse of overflow of counters 7 and 8) and issues it to the input of the block 4. Under the action of this pulse, the block 4 forcibly forms a reading of the measured parameter, which fixes as a significant one, and brings nm pulses to the input of the trigger 10, under the action of a clock pulse from chronizate Ora 1 delivers pulses to the input of encoder 2 and elements 11 and 12, and the value of reference to input of encoder 3. Then the full code from the output of the imager, similar to the full code of significant reference, goes to the output of the device. This ensures an unambiguous measurement of the time intervals between significant readings and, as a result, the correct dating of the transmitted information.

The time interval encoding unit 6 operates as follows. At the moments of occurrence of real time readings, the state of trigger 10 changes, the outputs of trigger 10 change voltage levels at one output from low (zero) to high, at the other - from high to low (zero), and then vice versa . Under the action of the rising edge (from zero to zero to high) of trigger signals 10, sent to triggering inputs of one 7 and stopping inputs of another 8 counters, which start or end the counting of pulses arriving at their inputs from chroniser 1, while trigger 10 output high level signals control the passage of pulses from block 4 through elements 11 and 12.

Upon receipt of a pulse from block 4 to the input elements And 11 and 12, it passes through the corresponding element And 11 or 12 to the read input of the corresponding counter 7 and 8, which

finished counting, and reads from it the results of measuring the time interval between samples. The code combination corresponding to the measured time interval between the true moments of occurrence in the block of readings from the output of counters 7 and 8 through the OR element 9 enters the output of the block of bits of the bit outputs of the register 14 and composes the codes corresponding to the number (sum) and my received at the counting input of register 14 after the arrival of a signal (rising edge) received at the first input of counter 7 (8). The input pulse account

6. Immediately after turning on the hook 7 (8), it sets the trigger 22

The devices (supplying the supply voltage to it) of the counter elements (triggers, registers) can be in an arbitrary state.

in edtshichnoe state. The high potential from the output of the trigger 22 permits the passage through the element And 21 pulses coming from the counting input

To exclude the indefinite-15 and the counter 7 (8) to the input element And

together with the first significant count given by the device immediately after it was turned on, an asymmetrical trigger 27, which prevails on the zero side and is set to zero after the device is turned on, and the And 26 element. the state of the trigger 27, the zero-level signal from the output of the trigger 27 prohibits the passage of signals from the output of the elements OR 18 through the element AND 26.

When the block, after the device switches on the first significant measurement of the measured parameter, switches from the output of the block 6 to the input of the trigger 10 a pulse arrives that changes its state. The rising edge of the signal received from the output of trigger 10 to the first (start) input of one counter 7 (8) and to the second (stop) input of another counter 8 (7) phases all the elements of one counter (i.e., sets divider 23 to the original soy- 40 high potential.

this, triggers 25 and 27 in one

state, register 14 to the state .00 ... O, register 19 to the state 00 ... 01, at the output of the register 19 connected to the input of the element And 20, a high potential acts, then a high potential). As a result, the outputs of the elements 16 when polled as well Thus interrogate the register 14 through the elements And 16. At the same time, if the inputs of the elements And 16 connected to the outputs of the register 14,

Those counter starts the correct counting counting calculation and stops another counter.

In the running counter 7 (8), the register 14 counts the pulses received at its counting input before the signal 7 (8) arrives at the second input, which by the rising edge of the level puts the trigger 25 into the zero state, which prevents the passage of counting hectares of pulses through the AND element 24 to the input of the counting register 14. Register 14 terminates the account.

in edtshichnoe state. The high potential from the output of the trigger 22 allows the And 21 pulses through the element to flow from the counting input 21. The first pulse that passed through the AND 21 element returns the trigger 22 to the initial state (thus prohibiting further passage of the pulse

via element 21 and 21) -, phases the shift register 19 (i.e., state 100 ... O is set in register 19). The zero potential from the output of the register 19 permits the passage through the AND 20 element of 1-M pulses coming from the counting input of the counter 7 (8) to the input of the AND 20 element. The pulses passed through the AND 20 element are fed to the shift input of the register 19

and produce register 19. Due to the fact that the first input of register 19 is connected to the tire of zero potential, register 19 produces

the unit shift from low to high, i.e. at each, also, a shift in series in time at the outputs of register 23, including those connected to the inputs of the grz ppa 15 of the elements 16, appears and disappears

a high potential acts, then at the outputs of the elements 16, when polling, the register 14 is thus interrogated through elements 16. At the same time, if the inputs 16 of the elements 16 connected to the outputs of register 14,

there is a high potential as well. if the indicated inputs of the elements And 16 place zero potential,

50 then when polling at their outputs there will be zero potential. The signals from the output of the elements And 16 arrive through the element liJlI-i 18 and the element And 26 to the output of the counter 7 (8). At the output of the counter

55 7 (8), the signal levels are consistently reversed in time, corresponding to the bit outputs of the register signals 14, the levels of which are a combination of the signals corresponding to the sum of the pulses received at the counting input of the register 14 for the duration of the time interval between the significant samples.

At the end of the survey, register 14, which corresponds to the time reached, nor by the shifted unit of output of the higher bit regregstra 19, i.e. shift register 19 goes to state 00 ... 01, zero potential is set at the output of counter 7 (8), a high potential from register 19 output connected to input of element I 20 prohibits further propagation of pulses through element 20 to shifting the second input of the register 19 shift

When reading from the other 8 (7) counter of the code combination about the time interval corresponding to the first significant parameter reading after switching on the device, the zero state of the trigger 27 prohibits the passage of signals from the output element OR 18 through the AND 26 element. -9 of the full count code corresponding to the first significant count after the device was turned on, zero value of the measured time interval. This makes it possible to distinguish the first significant count from other readings, as well as fixing the time scale in which the device measures the parameter.

The decoder 28, connected to the outputs of the register 14, decrypts the code combination of the signals acting on the outputs of the register 14. The decoder 28 is configured to the code combination of signals preceding E, overflow of the counter 7 (8). When register 14 reaches the specified state, the decoder 28 generates a high level signal to the input of the pulse former 17, which, on the rising edge of the input signal, generates an impulse to stop the time interval measurement by this counter and sends this pulse to the output of the counter 7 (8). Thus, the proposed device provides measurement of the time intervals between significant readings with high accuracy, which increases the reliability of information transmission.

ABOUT

O Z d

five

Claims (1)

1. A device for transmitting messages in adaptive telemetry systems comprising a chronizer, the first output of which is connected to the first inputs of the information redundancy reduction block, address encoder and information encoder, the first, second outputs of the information redundancy reduction block are connected respectively with the second input of the information coder and the combined second input of the address coder and the first inputs of the first and second elements And, the outputs of the information encoder and the interrogation encoder are connected respectively to the first and second inputs of the message code generator, the third output of the information reduction block is connected to the connecting inputs of the trigger, the first and second outputs of which are connected to the second inputs of the first and second elements AND, respectively, whose outputs are connected to the first inputs of the second and first binary counters, respectively For the first time, the outputs of which are connected to the same inputs of the first OR element, the output of which is connected to the third input of the message code generator, the second input of the information redundancy reduction unit and the output of the message code generator are the input and output of the device, respectively, the second output of the synchronizer is connected to the combined second inputs binary counters, due to the fact that, in order to increase the reliability of messages and simplify the device, a second OR element is introduced into it, the output of which is connected to th input block redundancy information abbreviations third and fourth Rin ode binary counters respectively combined and connected respectively to first and second outputs of the flip-flop, outputs of first and second binary counters are connected vtorgo with similar inputs of the second OR gate. 2, The device according to claim 1, that is, that the binary counter is executed on triggers, registers, decoder, pulse shaper, frequency divider, AND elements, OR element, AND group of elements and zero potential bus, first trigger output connected to the first input of the first element I, the output of which is connected to the first input of the first register, the outputs of which are connected to the first inputs of the same name elements of the group and the corresponding inputs of the decoder, the output of which is connected to the input of the pulse former, the output is second the trigger is connected to the first input of the second element, the output of which is connected to the first input of the second trigger and the first input of the second register, the first outputs of which are connected to the second inputs of the elements of the same name AND group, the outputs of which are connected to the corresponding inputs of the element OR the output and output of the third trigger connected to the first and second inputs of the third element AND, respectively; the output of the third element AND and the output of the pulse former are respectively the first and second the outputs of the binary counter, the second output of the second register is connected to the first input of the fourth element And, the output of which is connected to the second input of the second register, the third input of which is connected to the zero potential bus, the fourth input of the second register is combined with the input of the third trigger, the first input of the first trigger, the first input of the frequency divider and the second input of the first register and is the first input of the binary counter, the second input of the first trigger and the second input of the second trigger are respectively the second and third inputs of the binary counter, the output of the frequency divider is connected to the second input The first element And, the second inputs of the frequency divider, the second and third elements And are combined and are the fourth input of the binary counter. 5te /