SU862373A1 - Device for synchronous information asynchronous input/output - Google Patents

Description

The invention relates to a wired telecommunication technique, can be used in equipment for asynchronous input-output of synchronous binary information into digital channels of systems with pulse-code modulation and delta-modulation.

A device for asynchronous input-output of synchronous information * containing a controlled distributor on the transmitting side * whose outputs are connected to the corresponding inputs of the memory unit, and on the receiving side are serially connected clock generator, controlled distributor and memory unit, as well as a phase decoder whose output is connected with an additional input of the memory unit [C.

However, the known device has a low bandwidth.

The purpose of the invention is to increase throughput.

To do this, to the asynchronous input-output device of synchronous information containing a controlled distributor on the transmitting side, the outputs of which are connected to the corresponding inputs of the memory unit, and on the receiving side there are serially connected clock frequency generator, controlled distributor and memory unit, as well as a phase decoder, output which is connected to the additional input of the memory block, you enter on the transmitting side a start-up and control block, a forecast control and correction block, a binary-decimal converter and a bl to the recurrence of shift registers having a first input connected to the output of the BCD converter, a first input of which is connected to an additional input of the storage unit, the first output start and control unit and the second input of the recurrence of shift registers, the third input of which is connected to the second output of the ³ 862373 start-up and control, the third and fourth outputs of which are connected respectively. respectively, with the first and second inputs of the controlled distributor, the first output of the memory block connected to the second input of the binary-decimal converter, the second output of the memory block connected via the forecast control and correction block to the fourth input of the block of recurrent shift registers, and the second input of the control and forecast correction block connected to the third input of the start-up and control unit, and on the receiver side, the start-up and control unit, the recurrence recognition unit, and the deviation analysis unit are connected in series. '' from the forecast, the forecast correction block and the regular forecasting block, the output of which is connected to the input of the clock generator. In this case, the second input of the controlled distributor is connected to the second output of the start-up and control unit and the second inputs of the regular forecasting unit and the recurrence recognition unit, the second output of which is connected to the input b <start-up and control ', the first output of which is connected to the first input of the phase decoder, the second whose input is connected to the third output of the recurrence recognition unit, and you

IS

A synchronous binary signal following with a clock frequency f _c is input into a digital communication channel characterized by a carrier frequency Ec. This operation is carried out on the transmitting side (Fig. 1). In accordance with the selected length of the information cycle, in the start-up and control unit 3, frequency reference signals f _H / N are formed from frequency signals, where N corresponds to the number of bits. Supporting them. J pulses starts the controlled distributor 2, which is then clocked by clock pulses. The pulses from the output of the controlled limiter 2 are used for synchronous binary signals in memory 1.

The number of pulses recorded by the memory depends on the phase relationship of the frequency signals and f _n , as well as on the possibilities of deviation of the frequency signals fc. This number can be equal to p-1, η or n + 1. The number of pulses. in the information cycle formed on the transmission and its correspondence to the forecast · is controlled by the forecast control and correction unit 6, which is started and controlled by the reference pulses from the start and control unit 3. The algorithm for this control is illustrated in the table.

- 'C · record block to block the course of the forecast correction block is connected

with the second input of the analysis deviation analysis block, the second output of which is connected to the third input of the block Pseudorandom Selection Algorithm 35 sequences regular forecasting. number Actual Decision In FIG. 1 presents structural pp bit d in quantity about number transmission circuitry formation bit in selected us of the proposed device; figure 2 40 nom cycle formation pseudo-case same, the receiving side. (by nom the cycle tea Asynchronous input-output device gnosis) investigator the synchronous information water contains on the transmitting side a memory unit 1, nosti 45 • controlled distributor 2, block 3 launch and control, binary ten 1 n-1 n-1 1 tical converter 4, ΐσϊοκ_5 recurrent shift registers, block 6 cont 2 n-1 η eleven the role and correction of the forecast, on the receiving side (see Fig. 2) - block 7 recurrence recognition, block 8 start fifty 3 η η 1 and management, block 9 analysis of the deviation from the forecast, block 10 regularly 4 η η-1 1 1 1 th forecasting, block 11 forecast correction, generator 12 clock 55 5 η η + 1 eleven toots, controlled distributor 13, memory unit 14, phase 15 decoder. 6 η + 1 η + 1 1 The device operates as follows 7 η + 1 η 1 1 1

at once.

If the deviation from the forecast occurs in several (successively following) cycles and in the same direction, the block 6 control and correction of the forecast adjust the predicted sequence ₅ on the transmission. Synchronous binary signals recorded in memory unit 1 at a clock frequency f _c are read from there by fast clock pulses (BTI) coming from control unit 3 and processed in binary-decimal converter 4. The converter converts the information cycle from binary to decimal . The maximum length of the information “P ++ cycle in decimal code is 2,

those. the number of time positions allocated for the transmission of information in this cycle in the binary code is always equal to n + 1.

Depending on the presence or absence of a deviation from the predicted number of bits in the information cycle, a pseudorandom sequence I, II, or III is selected in block 5 of the recursive shift registers. Under the action of fast clock pulses and in accordance with the signals from the output of the binary-decimal converter 4 in the block 5 of the recurrence shift registers, the initial phase of the selected pseudo-random sequence is shifted. The sequence from block 5 of the recurrence shift registers is read at the carrier frequency f _{H of} the communication channel. The length of the pseudo-random sequence section transmitted to the channel is selected taking into account the need to protect information from single errors.

z

The digital sequence from the communication channel is fed to the input of the receiving side (Fig. 2). Before transmission begins, a pseudo-random sequence with a phase shift that is not usually used in operation is formed on the transmitting side. At the receiving side, the initial phasing of the reference pulses occurs along the received and recognized portion of this pseudo-random sequence. frequency f _H / N and starts the unit 8 start and control. This unit generates reference pulses and fast clock pulses, which are further used in the work of the receiving side.

With the arrival of a section of a pseudo-random sequence that carries useful information, the recurrent recognition unit 7 determines the number (I, II or III) of the pseudo-random sequence. This operation is performed in the Case of receiving an error-free section of a pseudo-random sequence or receiving a section in which there is a single error. Depending on which of the pseudo-random sequences was used in the transmission, the corresponding signal is sent to the deviation analysis block 9 from the forecast and then to the regular prediction block 10. In addition, this signal is stored in the prediction correction block 11. Block 11 captures the deviation from the forecast in one direction in several (consecutive following) cycles and makes a decision to change the forecast, for which it sends the corresponding commands to block 9 of the analysis of deviations from the forecast and to block 10 of regular forecasting. Note that the start of operation of block 10 is determined by the reference pulses coming from block 8 start and control,

The signal from the output of the regular forecasting unit 10 (corrected, if necessary, by commands from the output of the deviation analysis from the forecast 9 or by the commands from the output of the forecast correction unit 1I) is supplied to the clock frequency generator I2 and adjusts the frequency of the generator within the information cycle so that the number of bits in a cycle on the receiving side was equal to their number on the transmitting side.

The recognized section of the pseudo-random sequence, carrying useful information, is analyzed in the phase 15 decoder, where the initial phase of the recurrence section is determined in decimal code, which is then converted to binary code. - The decoder operates with fast .tak pulses.

Presented in binary code, the loop information enters the memory unit 14 at a speed corresponding to the carrier frequency ^ of the communication channel.

From the memory block, the binary signals of the information cycle are read by the pulses of the corrected clock frequency f _c coming through the controlled distributor 13 from the output of ge55

862373 8 • non-clock frequency 12. The cyclic operation of the controlled distributor 13 is determined by the reference pulses from the output of the start and control unit 8. The signals from the output of block _{5 of the} memory 14 at a clock frequency fg enter the subscriber line.

Thus, in the proposed device for the asynchronous input (output) of synchronous binary information into the digital communication channel, service information is transmitted by selecting various pseudorandom sequences, which provides a gain in the use of channel bandwidth.

Claims (1)

The invention relates to a technique of wired telecommunications, can be used in the equipment of asynchronous input-output of synchronous binary information into digital channels of systems with pulse-code modulation and division-modulation. A device for asynchronous I / O of synchronous information is known, containing on the transmitting side a controllable distributor whose outputs are connected to the corresponding inputs of the memory unit, and on the receiving side - a serially connected clock generator, a controllable distributor and the memory unit, as well as a decoder phase, the output of which is unified with the auxiliary input of the DL memory block. However, the known device has a low:) throughput. The purpose of the invention is to increase throughput. For this purpose, an asynchronous input-output device of synchronous information containing a controllable distributor on the transmitting side, the outputs of which are connected to the corresponding inputs of the memory block, and on the receiving side - a serially connected clock generator, a controlled distributor and the memory block, and a phase decoder, the output of which is connected to the memory input of the memory unit, will enter on the transmitting side a startup and control unit, a prediction control and correction unit, a binary-to-ten converter and a b Lock of recurrent shift registers, the first input of which is connected to the output of a binary-decimal converter, the first input of which is connected to the additional memory input, the first output of the starting and control unit and the second input of the recurrent shift register unit, the third input of which is connected to the second output of the block 3 : 8 start-up and control, the third and fourth outputs of which are connected respectively. Respectively with the first and second inputs of the controlled distributor, the first output of the memory unit is connected to the second input of the binary-decimal converter, the second output of the memory unit is connected through the control and correction unit to the fourth input of the recurrent shift register unit, and the second input the prediction control and correction unit is connected to the third version of the launch and control unit, and on the receiving side, the serially connected launch and control unit is inserted, the recognition unit, not the recurrent, the analysis unit, deviation e- 1n from the forecast, the forecast correction block and the regulating block of forecasting, the output of which is connected to the input of the clock frequency generator. The second input of the controlled distributor is connected to the second output of the start-up and control unit and the second inputs of the regular prediction block and the recurrence recognition unit whose second output is connected to the input of the start-up and control unit, the first output of which is connected to the first input of the phase decoder, the second input which is connected to the third output of the recurrent recognition block, and the output of the forecast correction block is connected to the second input of the deviation analysis block, the second output of which is connected to the third im input of regulator molecular predictor. FIG. Figure 1 shows the structural electrical circuit of the transmitting side of the proposed device; 2, the receiving side. The asynchronous I / O device of synchronous information contains on the transmitting side the memory block 1, the controlled distributor 2, the start-up and control unit 3, the binary-decimal converter 4, the recurrent shift registers, the control and prediction correction unit 6, on the receiving side ( see Fig. 2) - recurrence recognition unit 7, start and control unit 8, deviation analysis analysis block 9, regular prediction block 10, forecast correction block 11, clock frequency generator 12, controllable distributor 13, memory block December 14 Oder phase 15. The device operates as follows. 3 A synchronous binary signal, with the next clock frequency f, is introduced into the digital communication channel, characterized by the carrier frequency f. This operation is carried out on the transmission side (Fig. 1). In accordance with the selected information cycle dandy, in the run and control unit 3, frequency signals are generated from the frequency signals f c, where N corresponds to the number of bits. The reference im- .. J pulses start the controlled distributor 2, which is then clocked by pulses of the clock frequency f. The pulses from the output of the controlled distributor 2 are used to write synchronous X binary signals into memory block 1. The number of pulses recorded into the memory block depends on the phase ratio of the signals of the frequency f and f, as well as on the possible deviation of the signals of the frequency fc. This number may be p-1, n, or n + l. The number of pulses. in the information cycle generated on the transmission and its correspondence to the forecast is monitored by the forecast monitoring and control unit 6, which is started and controlled by the reference pulses from the start and control unit 3. The algorithm of this control is illustrated in the table. Algorithm for choosing a pseudo-random sequence If the deviation from the forecast occurs in several (additional next) cycles and in the same direction, block 6 of the control and correction of the forecast corrects the predicted sequence in the transmission. Synchronous binary signals recorded in the memory at the clock frequency f are read out from there by fast clocks (VTI) received from the start-up and control unit 3, and are processed in the binary-decimal converter 4. The converter translates the information cycle from the binary code in decimal. The maximum length of the information cycle in decimal code is i.e. the number of time positions allocated for transmission of information in this binary code is always equal. Depending on the presence or absence of a deviation from the predicted number of bits in the information cycle in block 5 of the recurrent shift registers, pseudo-random sequence I, II or III is selected. Under the action of fast clock pulses and in accordance with the signals from the output of the binary-decimal converter 4 in block 5 of the recurrent shift registers, the initial phase of the selected pseudo-random sequence shifts. The sequence from block 5 of the recurrent shift registers is matched at the carrier frequency f of the communication channel. The length of the pseudo-random sequence transmitted into the channel is chosen taking into account the need to protect information from one-time errors. The digital sequence from the communication channel is fed to the input of the receiving side (Fig. 2). Before the transmission begins, a pseudo-random sequence is formed on the transmitting side with a phase shift that is not normally used in the work. On the receiving side, according to the received and recognized part of this pseudo-random sequence, the initial phasing of the reference pulses occurs. frequency f / N and starts the block 8 start and control. This block generates support pulses and fast clock pulses used later in the work of the receiving side. With the arrival of a portion of a pseudo-random sequence carrying useful information, the recognition unit 7 recurrent determines the number (I, II, or AND I) of the pseudo-random sequence. This operation is performed in the case of receiving an error-free portion of a pseudo-random sequence or a reception portion in which there is a one-time error. Depending on which of the pseudo-random sequences was used in the transmission, the corresponding signal is sent to the deviation analysis analysis unit 9 and then to the regular forecasting unit 10. In addition, this signal is stored in the prediction correction block 11. Block 11 records the deviation from the forecast in one direction in several (next next) cycles and makes a decision to change the forecast, for which it sends the corresponding commands to the deviation analysis block 9 from the forecast and to the regular forecast block 10. Note that the start of operation of block 10 is determined by reference pulses from the start and control unit 8, the signal from the output of block 0 of the regular prediction (corrected, if necessary, by the commands from output 9 of the deviation analysis from the forecast or by the commands from the output of block 1I of the forecast correction) enters the clock frequency generator 12 and adjusts the oscillator frequency within the information cycle so that the number of bits in the cycle on the receiving side is equal to their number on the transmitting side. The recognized portion of the pseudo-random sequence carrying useful information is analyzed in a phase 15 decoder, where the initial phase of the recurrent portion in the decimal code is determined, which is then transcoded into a binary code. The decoder operates with fast clocks. The cycle information presented in binary code enters the block 14 at a speed corresponding to the operating frequency f of the communication channel. The binary signals of the information cycle are read from the memory block by pulses of the corrected clock frequency f (; received through the controlled distributor 13 from the output of the clock frequency generator 12. The cyclical operation of the controlled distributor 13 is determined by reference pulses from the output of the start and control block 8 Signals from the output of the memory unit 14 at the clock frequency fg are fed to the subscriber line. Thus, in the proposed asynchronous input device (synchronous input) of synchronous binary information into the digital communication channel service information is transmitted by selecting different pseudo-random sequences, which ensures a better use of channel capacity. Formula of the Invention Asynchronous I / O synchronous information device containing on the transmitting side a controlled distributor, the outputs of which are connected to the corresponding inputs of the memory unit, and on the transmit side side connected in series clock generator, controlled, distributed spruce and memory block, as well as a phase decoder, the output of which It is connected to an additional input of a memory unit, characterized in that, in order to increase capacity, a start-up and control unit, a prediction control and correction unit, a binary converter and a recurrent shift register unit are entered on the transmitting side, the first input which is connected to the output of the binary inverter, the first input, which is connected to the auxiliary input of the memory unit, the first output of the starting and control unit, the second input of the recurrent shift register unit, the third input of which It is connected to the second output of the start-up and control unit, the third and fourth outputs of which are connected respectively to the first and second inputs of the controllable distributor, the first output of the memory unit connected to the second input of the Binary-decimal converter, the second output of the block i is connected via the control and prediction correction block to the fourth input of the recurrent shift register block, and the second input of the forecast control and correction block is connected to the third output of the check and control block, and on the receiving side A start and control unit, a recurrence recognition unit, a deviation analysis unit, a forecast correction unit, and a regular prediction unit, the output of which is connected to the clock generator input, are connected in series with the second input of the controllable distributor and control and the second inputs of the regular prediction block and the recognition block recurrent, the second output of which is connected to the input of the start and control unit, the first output of which is connected the first input of the phase decoder, the second input of which is connected to the third output of the recurrent recognition unit, and the output of the prediction correction block is connected to the second input of the deviation analysis block, the second output of which is connected to the third input of the regular prediction block. Sources of information taken into account during the examination 1. USSR author's certificate No. 510792, cl. H 04 J 3/00, 1974 (prototype). I F h V four . bs.