SU826343A1 - Multiplier of periodic pulse repetition frequency - Google Patents

Description

The invention relates to automation and computer engineering and can be used in processing information presented in the form of periodic frequency-pulse sequences. ^s

Known frequency multiplier, co. holding control unit, clock generator, frequency divider, counter, register, adder, comparison unit, AND and OR elements, trigger ¹⁰ and delay element [4

Also known is a frequency multiplier containing a pulse shaper, a control unit, a clock pulse generator, a frequency divider, counters * ⁵ clocks, a register, an AND and OR element, a key one-shot P1.The disadvantage of these devices is the lack of binding of output pulses to pulses of a multiplied frequency.

Closest to the proposed one is a periodic pulse repetition multiplier comprising a clock pulse generator connected by an output to the counting input of the first frequency divider, connected by an output to the counting input of the first counter, the output of which is connected to the information input of the first register, connected by the output to the first input of the comparison unit codes connected by the second input to the output of the second counter, and by the output to the first input of zeroing the second counter, the first input of the first AND element and to the counting input the second frequency divider connected by the output to the first input of the trigger, connected by the output to the second input of the first AND element, the output of which is connected to the first input of the OR element, connected by the output to the output bus of the multiplier, the second input of the OR element, the second trigger input, the control input of the first register, the second zeroing input of the second counter and the zeroing inputs of the first counter and frequency dividers are connected to the input bus of the multiplied ”frequency, and the counting input of the second counter is connected to the output of the clock generator pulses [3].

The disadvantage of this device is the reduced accuracy of the multiplication due to the uneven sequence of the output pulses of the multiplied frequency.

The purpose of the invention is to increase the accuracy of multiplication.

This goal is achieved by the fact that the pulse repetition frequency multiplier comprising a clock pulse generator connected by an output to the counting input of the first frequency divider, connected by an output to the counting input of the first counter, the output of which is connected to the information input of the first register, connected by the output to the first input of the comparison unit codes connected by the second input to the output of the second counter, and the output to the first input of zeroing the second counter, the first input of the first AND element and to the counting the input of the second frequency divider connected by the output to the first input of the trigger connected by the output to the second input of the first AND element, the output of which is connected to the first input of the OR element connected by the output to the output bus of the multiplier. Moreover, the second input of the OR element, the second trigger input, the control input the first register, the second zeroing input of the second counter and the zeroing inputs of the first counter and frequency dividers are connected to the input bus of the multiplied frequency, the synchronization block, adder, second and third registers and the second are entered And element connected by the output to the counting input of the second counter, the first input to the output of the clock generator, and the second input to the output of the synchronization unit, the control input of which is connected to the output of the clock generator, the zeroing input is the output of the code comparison unit, and the information input - with the output of the senior bit of the adder connected to the first and second inputs to the information outputs of the second and third registers, respectively, and the outputs of the remaining bits to

826343 4 to the information input of the third register, the control input of which is connected to the output of the code comparison unit, the information input of the second register is connected to the code output of the first controllable frequency divider, and the control input of the second register and the reset input of the third register are connected to the frequency input bus 10.

The drawing shows a block diagram of a multiplier of repetition frequency of periodic pulses, ¹⁵ The multiplier contains a clock generator 1, connected by an output to the counting input of the first frequency divider 2, the output of the divider 2 is connected to the counting input of the first η

counter 3, the output of which is connected to the information input of the first register 4, the output of register 4 is connected ·. with the first input of block 5 code comparison. Block 5 is connected by the second input ²⁵ to the output of the second counter 6, and the output to the first input of zeroing the counter 6, the first input of the first element And 7 and to the counting input of the second frequency divider 8. The output of the divider 8 is connected to the first input of the trigger 9, connected by the output to the second input of the element And 7. The output of the element And 7 is connected to the first input of the element OR 10, the output of which ^{35 is} connected to the output bus of the multiplier. The second element And 11 is connected by the output to the counting input of the counter 6, the first input to the output of the generator 1, and the second input to the output of the block ⁴⁰ 12 synchronization. Block 12 is connected to the control input with the output of generator 1, the zeroing input to the output of block 5, and the information input to the high-order output of adder 13. The adder 13 is connected by the first and second inputs to the outputs of the second and third registers 14 and 15, respectively, and the outputs of the rest discharges - to the information input re ^{50 of the} histogram 15. The control input of the register 15 is connected to the output of block 5. The information input of the register 14 is connected to the first output of the divider 2. Inputs for resetting the counter 3, dividers 2 and 8 and register 15, the second input for resetting the counter 6, the control inputs of registers 4 and 14, the second input ^ of trigger 9 and the second input of the element

OR 10 is connected to the bus 16 input frequency multiplier.

The frequency multiplier operates as follows.

The current pulses of the period T _o with the output _{5 of the} generator 1 are supplied through a divider 2 with a division factor K equal to the required multiplier coefficient of the multiplier to the input of counter 3. After a period of time equal to the period of the multiplied frequency, in counter 3 and in divider 2 will be the whole and fractional parts, respectively, of dividing the number of pulses received at the 15th input of divider 2 by the coefficient K are fixed. At the end of the first period of the multiplied frequency, these results are respectively transferred from divider 2 to register 14, and from counter 3 - 2 0 to register 4. At the same moment, register 15 and counter 6 are reset.

In the second period, counter 3 counts in the same way, and the result recorded in register 4 is compared by block 5 with the current value of the number of pulses counted by counter 6. At the moment of matching codes at the inputs of block 5, a pulse is generated at its output, which triggers 30 counter 6 and through the elements And 7 and OR 10 passes to the output bus multiplication. If at the same time the element And 11 is open during the entire period of the multiplied frequency, then the pulses at the output _{3S of} block 5 appear at time intervals d t = [^ -] T _O , where [the integer part of the ratio. As a result, on the device output bus, every i-th pulse appears ahead of (by mistake) by the time ^β | · κ | Τ _ο · Ι, · where is the fractional part of the ratio.

The reduction of this error during operation of the device occurs as follows ₄₅ . Code ΔΝ remainder of dividing K * to output from the register 14 is supplied to a first input of the adder 13. On arrival of the first pulse output unit 5 the read I3 perepisi- _Μ INDICATES adder to the register 15 and output register 15 is fed to a second input of the adder 13 * Thus over a period multiplied frequency by the adder 13 adds the ₅₅ rows Ko residues, wherein the result is increased by AN with the arrival of each pulse from the output unit 5. If the current value of the sum thumbs residues creases number K, the output of the adder 13 starshegorazryada a signal is formed logical unit. This signal from the output of the adder 13 is fed to the information input of the block 12, initialized by a pulse from block 5 and controlled by the pulses of the generator 1. Block 12 generates a pulse with a duration of 1 ' _o , which closes _the element And 11 for a while, prohibiting the passage to the input counter 6 of one pulse from the output of the generator 1, As a result, pulses from the output of block 5 can appear ahead of no more than T _about .

To synchronize and tie the last output pulse to the end of the period of the multiplied frequency, the pulses from the output of block 5 are fed to the counting input of the divider 8 by a factor K. If K pulses have time to arrive at the counting input of the divider 8, and the period of the multiplied frequency has not yet ended, then the signal with the output of the divider 8 closes the element And 7 through the trigger 9 and stops the supply of pulses to the output bus of the multiplier.

Thus, the proposed device allows, in comparison with the known one, to reduce the unevenness of the output pulses and increase the accuracy of the multiplication.

Claims (3)

1. USSR author's certificate number 570064, cl. G 06 G 7/16, 1976. 2. USSR author's certificate number 576658, cl. H 03 K 5/01, 1976. 3. USSR author's certificate No. 498624, cl. G 06 F 7/39, 1970 (prototype).