SU822243A1 - Indication device - Google Patents

Description

(54) DEVICE FOR INDICATION

one

The invention relates to automation, computing and measurement technology and can be used. but for the visual presentation of information.

A device for indicating, containing gas-discharge digital lamps, whose cathodes are connected via a decoder to reading circuits associated with counting decades, a distributor and anode keys, whose outputs are connected to gas-discharge digital lamps anodes, a prohibition circuit whose output is connected to a valve, and one of the inputs is to the generator, the other to the time relay associated with the distributor and the photo sensor. This device allows you to adjust the brightness of the displayed information depending on ambient light.

A display device is also known that contains comparison circuits whose inputs are connected to registers, a code converter and a binary counter associated with a pulse generator, and the outputs of comparison circuits are connected to control electrodes of digital-synthesizing indicators, a pulse distributor and a block of elements I the inputs of which are connected to the code converter and the pulse distributor associated with the overflow output of the binary-decimal counter, and the outputs of the block of elements And are connected segments tsifrosinteziruyuschih indicators 2.

However, limiting the brightness adjustment range of an image-shaped image, associated with the number of characters of the 15 alphabet used, reduces the ability to select the optimum image brightness and contrast of this image relative to the background, corresponding to

this illumination in the room, where 20 a display device is operating,

and this negatively affects the perception and recognition of the output information by the operator. This limitation of the maximum value of the average luminance is especially noticeable in display devices that use character indicators with a large number of segments.

The purpose of the invention is to improve image clarity.

The goal is achieved by the fact that in a display device containing a comparison unit, one inputs of which are connected to registers, other inputs to the output of a code converter, and series-connected pulse generator, a counter connected to ONE of the code converter inputs, a pulse distributor connected to to another input of the code converter, and a interface unit, the output of which is connected to the characters of a syntax indicator, the control electrodes of which are connected to the outputs of the key element unit An additional memory block is added, the first input of which is connected to the output of the comparison unit, and the output of the memory block is connected to the input of the key element block and the delay block whose input is connected to the second input of the memory block and output of the counter, and the output of the delay block connected to the third input of the memory unit.

The drawing shows a block diagram of a device for indicating

The display device comprises a comparison unit 1, the first inputs of which are connected to registers 2, a distributor 3, to the input of which an overflow output of a counter 4 connected to a pulse generator 5 is fed, an interface 6, the outputs of which are connected to the segments of the synthesizing indicators 7, controlling electrodes of which are connected to the outputs of a block of 8 key elements, a block of 9 memory connected to the outputs of a block of comparison 1 and inputs of a block B of key elements, a converter of 10 codes whose inputs are connected to the distribution Telem 3 and source 4, and the output is connected to the second inputs 1 of the comparator, delay block 11, the output of which is connected to the inputs of memory block 9, and the input together with the clock inputs of memory elements 9 is connected to the overflow output of counter 4, and the distributor output 3 is connected to an interface block b.

Let us consider the principle of operation of the device for indication by the example of displaying digital information, represented by a binary decimal code 1-24-8, a nag-segment indicator.

Let register 4 contain the code for digit 4.

As the pulses from the generator 5 are received, the counter 4 is filled and at its outputs the output pulses arriving at the code converter 10 appear, and the overflow pulse of the counter 4 is fed to the input of the distributor 3 and synchronizes the operation of the counter and the distributor. The number of outputs of the distributor 3 is equal to the number of segments of the symbol-synthesizing indicator 7 (in the considered example 7). At each of the seven outputs of the distributor, pulses are formed, which through the block 6 of the conjugation carry out sequential excitation of the segments and indicators 7. At the same time, these pulses are fed to the converter 10 of codes. The distributor 3. forms a cyclic sequence of seven pulses, the duration of each of which is equal to the duration of one cycle of operation of the counter 4. At the end of the cycle, an overflow pulse causes the appearance of a pulse at the next output of the distributor 3, etc. In this case, during one cycle of operation of the distributor 3, all the first, then all the second, and so on are sequentially excited first. indicator segments 7. Depending on the signal from memory block 9, coming through the block of 8 key elements to control electrodes, the signs of synthesizing indicators 7, when this signal coincides with the excitation pulse of the corresponding segment, this element of the image is highlighted or not. Sequential highlighting of all elements of the image involved in the formation of the image of this sign on this indicator (figure 4 in this example) occurs in one cycle of operation of the distributor 3 or, identically, in seven cycles of operation of the counter 4 The number of outputs of counter 4 is equal to the maximum number of characters alphabet used, which must be compared with the information of registers 2 when the control signal is applied to the corresponding segment in accordance with the indicator control code. For example, it is advisable to use-. principle of quenching, so the number of outputs of counter 4 is six. The overflow signal of the counter may not coincide with the last output of the counter, since the polling signals of the registers 2 to form this image element are not associated in time with the indicator control signals. Therefore, the duration of the polling pulses of the registers is not limited by the frequency properties of the characterizing indicators, as in the known devices, and the frequency of the pulse generator can be chosen sufficiently large, not limited to the above properties.

The code converter 10 converts the signals arriving at its inputs from the distributor 3 and the counter 4 into a cyclically varying polling code in the form of a sequence of the binary-decimal code of the digits participating in the indicator control code in the formation of this image element. When arriving with the 3-pulse distributor, the 10-code-to-converter converter gives to the block of comparison circuits 1 a sequence of the binary-decimal code of numbers 1, 4 and 7, which participates in the formation of the image element. The sequence of issuing the code of these digits within the limits of the 10-code to the converter 10, the signal from the distributor and the counter may vary. When the pulse coincides with the distributor 3. and the pulse from counter 4, the binary-decimal code of digit 2 appears at the output of the converter 10 of the codes. In the rest of the time when the interrogation code does not appear at the output of the transducer, the converter of 10 codes in the considered case, it gives out a combination that is obviously absent in register 2, for example, 1-1-1-1, it is possible at this time to be interrogated by some combinations. With the output of the comparison unit 1, the pulses arrive at the inputs of the memory unit 9. When the code matches the polling with the information of register 2, a logical unit appears at the output of the first trigger of memory block 9, which means that when the next excitation control pulse of the next segment arrives, the signal at the control electrode of the indicator 7 should be absent and therefore The segment must be canceled. With the passage of the counter overflow pulse, signifying the end of the previous polling cycle and the beginning of a new, corresponding to the formation of the next image element, information from the first trigger of the memory block. These are rewritten into the second trigger, and so on. A logical zero appears at the output of the memory block, which locks the indicator 7 through block 8 of the key elements, and the first trigger of the memory block returns to the initial state. This trigger is again ready to receive information about the comparison result. In the absence of a pulse from the output of the comparison block I, a logical zero remains at the output during the polling cycle. With the arrival of the counter overflow pulse to the clock input-memory block 9, a logical unit appears at the output corresponding to the logical zero written from the first trigger of the memory block , while the control input of the indicator 7 receives an unlocking voltage and the indicator opens, since the arrival of a pulse means the beginning of the arrival of the control signal to the corresponding segment, the information about the required state which caused the signal to be unlocked on the control of the indicator 7 electrode electrode / the segment ignites, which should occur in accordance with the control and information code stored in this register 2. The third input of the memory block 9 is given a signal from the delay block 11 . Since, at a constant time cycle of operation of the counter 4 and a constant duration of control pulses, the average image intensity depends on the duration of the control pulses applied to the control electrodes of the indicators, the incoming signal ensures the formation of these control pulses. The signal at the output of the delay unit is formed by the phase shift of the counter overflow pulse. The amount of shift depends on the control signal and can be changed either manually or automatically, for example, according to the level of illumination in the room. The minimum shift is determined by the response time of the memory elements of block 9 and the frequency properties of the indicators. In the absence of a signal, the duty cycle of the control pulses will be minimal, and the duration of the control pulses fed to the control electrodes of the indicators will be. det is equal to the duration of control pulses arriving at the segments. In other cases, the duty cycle of control pulses will be greater (in this case, more than seven). When a signal arrives at the third input of the memory elements of block 9, a logical zero appears at its output, regardless of the state of the first trigger of the memory block. The indicator is locked and the corresponding segment, despite the control pulse continuing to flow to this segment, goes out. As a result of such a definite quenching of segments in accordance with the control and information code from this register 2, indicators 7 form an image of a given brightness: for the first cycle of the counter, all the first elements of the image of all indicators, for the second cycle, all second / and. etc., and in one cycle of operation of the distributor 3 - all the images in all the characters synthesizing indicators 7. The minimum period for which one image element is formed, i.e. the period of one cycle of operation of counter 4, provided that the counter produces per cycle counts, the number of which is equal to the number of outputs of the counter, for the considered variant is equal to six periods of the pulse from the generator. mpul.s, and the minimum period of the formation of the image of one character of the used alphabet is the 42nd period. Thus, the proposed device allows to increase the accuracy

the operator's perception of information, for visual presentation.

invention formula

A display device containing a comparison unit, one inputs of which are connected to registers, other inputs to the output of a code converter, and a series-connected pulse generator, a counter connected to one of the code converter inputs, a pulse distributor connected to another input of the code converter, and an interface unit, the output of which is connected to the seg, the cops of the sign-synthesizing indicator, the control electrodes of which

connected to the outputs of the block of key elements, characterized in that, in order to increase the image clarity, a memory block is inserted into it, the first input of which is connected to the output of the comparison block, and the output of the memory block is connected to the input of the block of key elements, and the delay block, the input of which is connected to the second input of the memory unit and the output of the counter, and the output of the delay unit is connected to the third input of the unit of power.

Sources of information taken into account in the examination

1: USSR Copyright Certificate 464904, 1974.

2. USSR author's certificate I 490144, 1974 (prototype).

Claims (1)

Claim A display device comprising a comparison unit, one input of which is connected to the registers, the other input to the output of the code converter, and a pulse generator connected in series, a counter connected to one of the inputs of the code converter, a pulse distributor connected to the other input of the code converter, and the interface unit, the output of which is connected to the segments of the sign-synthesizing indicator, the control electrodes of which are connected to the outputs of the block of key elements, characterized in that, in order to increase Nia-definition image, it entered the memory block, the first input coupled to an output of the comparator, and the output ⁵ of the storage unit is connected to the input of the key elements, and a delay block having an input connected to the second WMOs · home storage unit and the output of the counter and the output block delay connected to the third input of the memory block.