SU819947A1 - Storage device - Google Patents

Description

(54) STORAGE DEVICE

I

The invention relates to a radio communication technique and can be used in discrete information transmission systems with transmission rate adaptation. In these systems, when the propagation conditions of the signal or the interference level change, the transmission rate changes by changing the length of the transmitted symbol, and thus the required reliability of reception is ensured.

Accumulating devices are known for intermittent communication systems, or for systems with feedback information or decision 1.

This is either an electromechanical device such as tape recorders, in which the recording is made with one and the reading with a different speed, or purely electronic devices.

These electronic devices are memory blocks in which information is recorded at one speed and then read from these blocks at a different speed. The disadvantage of these storage devices is that they can operate only in either the recording mode or the read mode.

(if the read and write speeds are different). This prevents the use of such drives in systems with an adaptation of the transmission rate, where it is necessary to ensure reading during the recording process, and the reading speed can be both higher and lower than the writing speed.

The closest in technical essence to the invention is Avlosta storage device 2, which is a shift register in which are written

symbols information from the source of information.

At the time of the appearance of the communication channel (for example, in the meteor communication system), the message from the shift register goes to the exit at high speed. The reading is carried out all the time during which there is a communication channel. In this case, it may be that the drive was not completely filled, but only partially, and at the same time, the contents of the empty cells of the drive will be fed into the communication channel. In addition, this drive allows operation only in either writing to or reading from it, but it cannot work simultaneously in writing and reading. i.e., cannot work as part of a speed adaptive communication system.

The purpose of the invention is to engender simultaneous recording and reading.

The goal is achieved by the fact that a cumulative device containing a shift register, ha, is additionally introduced: a second shift register, a block of logical elements according to the number of register cascades, and an OR element. The inputs of the clock frequency of the registers are interconnected. The first outputs of all logic elements are connected to the inputs of the OR element. The second output of each subsequent logic element is connected to the first input of the previous one, the third output to the input of the zero setting of the corresponding bit of the second shift register. The second and third inputs of each logic element are connected respectively to the single and zero outputs of the corresponding bit of the second register, and the fourth input is connected to the single output of the corresponding bit of the first shift register. In addition, each logical element contains three two-input elements I. The input of the first element I is connected to the input of the second element I, the output of which is connected to the input of the third element I.

The functional diagram of the proposed device is shown in the drawing.

The device contains the first 1 and second 2 shift registers, logic elements 3 and the element OR 4. The device has an input 5 recording information in register 1 and an input 6 recording information in register 2. The clock inputs of registers 1 and 2 are interconnected and with the common clock input write pulses 7. The first outputs of each logic element of block 3 are connected to the inputs of the element OR 4. The first input of each logic element is connected to the second output of the subsequent element. The input of the first right logical element is the input of 8 read pulses, bus 9 is the information output, and the output of the last (left) logic element is output 10 of the indication of the absence of information in register 1. Bus 11 is the output of the drive overflow signal.

The third output of each logic element is connected to the installation input “About the corresponding bit from register 2, the second and third inputs of the logic element are connected to the single and zero outputs of the same bit, and the fourth input of each logic element is to the single output of the corresponding bit of register 1 .

Each logical element of block 3 contains elements AND. The first input element And 12 is connected to the fourth input of the logic element, the output - with the first output of the logic element, and the second

input - with the output of the element And 13 and with the third output of the logic element. The first inputs of the elements And 13y And 14 are connected with the first departure of the logic element, the second inputs - respectively with the second and

the third inputs of the logic element, and the output And 14 - with the second output of the logic element.

The device works as follows.

In the recording mode information characters

About from the source of information received at the input 5 of the register 1. At the input 7 receives the clock pulses, promoting simultaneously the contents of both registers. For example, if register 1 enters / C pulses

information, then in register 2 in the first K on the left cascades will be written “1. At the same time, in the right cells of both registers, the remaining "O."

For example, input 8 receives read pulses. If in the rightmost cascade of register 6 is written “O, this means that information is not recorded in the corresponding cascade of register 1”. Since at the same time the input element And 14 filed with the last cascade of register b permitting

potential, and the input And 13 - prohibiting, then the pulse from the input 8 passes through the element And 14 to the second output of the logic element and enters the first input of the next (to the left) logic element. If the corresponding cascade of register 2 also contains “O, then, similarly to the above, this pulse

go through the element AND 14 to the next logical element, and so on until it reaches the logical element that is connected to that cascade of the register 2, in which "1.

In this case, the resolving element is given to the And 13 element, and the forbidding potential is given to the And 14 element. The read pulse that passed from input 8 passes through the element.

0 And 13 and then goes to the installation “About the corresponding cascade of register 2, as well as to the element 12, which is connected to the corresponding cascade of register 1. If this cascade contains“ 1, then the resolving potential is fed to the element 12 ”

5 and the pulse C of the element AND 13 passes through the element AND 12 to the first output of the logic element and from there to the input of the element OR 14 and further to the output 9.

Since, when reading information .. from register 1, the corresponding cascade of register 2 is zeroed, the next read pulse of I and input 8 passes through AND 14 elements to the next logical element, and the reading is the same as described above.

Claims (2)

5 Thus, the reading of information from the accumulator (register 1) does not always start from the rightmost cascade, but from the one in which the first symbol of information is actually written, which is indicated by the first unit in register 6, encountered by a read pulse on its path. This allows the channel to be immediately loaded with useful information. In addition, the write (input 7 pulse shear) and read (input 8 shear pulse) circuits are separated, and therefore both processes can proceed simultaneously and independently. In this case, the necessary pulses at inputs 7 and 8 did not coincide. For this, non-multiple recording and interrogation frequencies are selected or frequency matching schemes are used. In the case of coincidence, the frequency arrives at input 7 with a delay determined only by the speed of the selected elements. The appearance of the signal at output 10 indicates that the interrogation signal from input 8 passed through all the logic elements 3, therefore, in register 1 there is no useful information and the communication channel can be used for other purposes. The appearance of the signal at output 11 indicates that all cells of register 1 are filled with information and you should either stop the source of information or switch it to another drive. The proposed device can be used in adaptive-speed communication systems, where the communication channel exists continuously, but changes over time, so that these systems constantly record and read information from a variable-speed storage device. The proposed device does not load the communication channel by transmitting "idle positions on which no information is contained. This increases the utilization rate of the communication channel. Claim 1. A storage device containing a first shift register, one input of which is an information input, and a second input - an input of clock pulses, characterized in that, in order to provide simultaneous recording and reading of information, a second shift register is additionally introduced into it, n logic elements and an OR element, while the clock outputs of both shift registers are interconnected, the first outputs of all logic elements are connected to the inputs of the OR element, the second output of each subsequent The logic element is connected to the first input of the previous one, the third output is connected to the input of setting zero of the corresponding bit of the second shift register, the second and third inputs of each logic element are connected respectively to the unit and zero outputs of the corresponding bit of the second shift register, and the fourth input of each logical element is connected to the unit output of the corresponding bit of the first shift register. 2. The device according to claim 1, characterized in that each logic element is made in the form of three two-input elements AND, while the input of the first element And is connected to the input of the second element And, the output of which is connected to the input of the third element I. Sources of information received into account during the examination 1. Transfer of information with a reverse zyu. Under. ed. E. M. Kanevsky M., Sv z, 1976. 2.Zaezdny AM and others. Methods of accumulation and their use in the processing of ignal. “Proceedings of educational institutions sv. Issue 51, 1970 (prototype).