SU817703A1 - Series-parallel action device for multiplying and dividing - Google Patents

Description

by the i-oro elements of the OR element, whose output is connected to the corresponding information input of the switch, the control inputs of the switch are connected to the corresponding control output of the shift distributor, the first output of the switch is with the counting input of the first counter of the digits (dividend), j-th outputs of the switch (j 2 (2n-1) - respectively with the first inputs) of the OR elements of the counting signals, the inputs of which are connected respectively to the counting inputs of the j-th counters of digits of the product (dividend).

The basis of the operation of the known device is the division method without restoring the residue. The method for calculating the product is similar to the method for calculating quotient 2,

However, the speed of the known device is limited by the transit time of the transfer signals in the bits of the multiplier (quotient) counter. Besides; the use of the counter cells of the product (divisible) counters and the delay cell of the clock device (divisor based on the number system) to eliminate the temporal imposition of pulses complicates the synchronization of the work of the individual nodes of the known device.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that in a device for multiplying and dividing a series-parallel action, containing a converter of digits multiplied (divisor) into a single code, reversible counters of digits of a multiplier (private), reversible Counters of digits of a product (divisible), trigger reverse, n groups (n - the width of the operands of the elements AND, n elements OR, commutator,. (2n-2) elements OR counting signals, n elements AND, shift distributor, pulse distributor and element NOT with the single output of the reverse trigger connected to the subtraction inputs of the reversible counters of multipliers (private) and the addition inputs of the reversible counters of the digits of the product Teremo), zero the output of the reverse trigger is connected to the inputs of the addition of reversible counters of digits of the multiplier (private) and the inputs of the reversible counters of digits of the product (divisible), the counting input of each reversible counter of digits Ithel (private) connected to the output of the corresponding, AND gate, a first input of each of which is connected to a control output distributor sootvetstvuyutsschm shift, the second input - with the output of the first pulse cycle pulse distributor, the first inputs of AND gates. groups (i 1, ... п) are connected to the corresponding outputs of the i-th group of converters of digits of the multiplicand (divisor) into a unit code, the second inputs of kx elements AND of each group (k 1, ... B), where base of the number system ) are connected to the corresponding synchronization outputs of the pulse distributor, the outputs of the elements of the i-th group are connected to the inputs of the i-element of the OR element, the output of which is connected to the corresponding information input of the switch, the control inputs of the switch, are connected to the corresponding outputs of the control of the shift distributor, The first output of the switch is connected to the counting input of the first digit counter of the (dividend) digits, the outputs of the switch (j 2, ... (2n-1)) are connected respectively to the first inputs (jl) -x of the OR elements of the counting signals, the outputs of which are connected respectively to the counting inputs JX of the digits of the digit (divisible) are additionally introduced transfer drivers, elements AND decryption of the code of zero reversible counters, and the OUTPUT of the first pulse of the pulse distributor cycle is connected to the input of the element NOT, the output of the element is NOT connected to the first clock input of the shift distributor and the polling input of the transfer former; the second clock input of the shift distributor is connected to the zero output of the reverse trigger; the zero outputs of the i-th reversible digit counters of the multiplier (private) are connected to the outputs of the elements AND code decryption of zero reverse digit counters of the multiplier (partial) , the outputs of which are connected to the corresponding inputs of the decoding of the zero code of the shear distributor. The outputs of the elements AND the decryption of the code of zero and -elements and the decoding of the B-1 code of the t-th reversing counts the digits of the digits of the (divisible) (t 1, .. 2p) are connected to the corresponding decryption code zero inputs and the B-1 code decoding inputs of the tth transfer drivers, the transfer outputs (jl) -x transfer drivers are connected to the second inputs of the corresponding elements OR, the transfer output of the (2n-1) th transfer generator is connected to the counting input of the 2nth product digit counter (divisible), the transfer output of the 2nth transfer driver is connected to the counting input of the reverse trigger, the first and second pass-through transfer ports of the 2nd transfer formers (., .. 2 p) connected to the corresponding outputs (2-1.) - of the transfer drivers, the control input of the 2th transfer driver is connected to the first control input of the shift distributor and is the input division of the device, the second control input of the distributor is input multiplying the device, the clock input of the pulse distributor is the clock input of the device, the output of the end of the shift distributor operation is the corresponding output of the device, the forward and inverse outputs of the reverse trigger are connected respectively to the input Dates of addition and subtraction of transfer drivers, bit outputs of t-th reversible counters of output (divisible) numbers are connected to the inputs of the corresponding elements AND decoding of the zero code and corresponding elements and decoding of the B-1 figure 1 shows a diagram of the proposed device ; in fig. 2 — transfer transfer pattern; Fig, 3 is a diagram of the shear distributor. The device contains a converter of 1 digit multiplier (divisor) into a single code, reversible counters 2 digits of the multiplier (private), reversible counters 3 digits of the product (divisible), trigger 4 reverse, p. groups of elements AND 5, n elements IL 6, commutator 7, elements OR 8 wired signals, n elements 9, distributor 10 shift, distribute 11 pulses, element 12, outputs 13 and 14 of the reverse trigger, output 15 of the first pulse of the cycle l 11, the outputs 16 of the control of the distributor 10 shift, the formers 17 of the transfer, the elements And 18 decryption code zero reversible counters 2, the elements And 19 and 20 decryption, respectively, zero code and code B-1 reversible counters 3 digits of the product, the input 21 dividing device , 22 multiply device input, clock input 2 3 devices, output 24, termination of the operation of the device, elements AND 25, elements AND-OR 26 of the switch 7. The transfer driver (figure 2) contains a D-flip-flop 27, elements AND 28-31, elements OR 32-35, element NOT 36. Distributor 10 shift (Fig. 3) contains a group of elements OR 37, a group of elements And 38-40, the OR 41 element, the AND 42 and 43 O-triggers of the 44 elements. In the proposed device, the multiplication operation is performed by repeatedly adding the multiplicand in the product counter. Multiplication by zero digits does not take time. Consider the operation of the device in multiplication mode. The multiplier is entered into converter 1, and the multiplier is entered into counter 2. Each group of outputs of converter 1 corresponds to the multiplier number and provides the resolving potentials for elements of AND 5 groups. The number of elements And 5 in the group is equal to B-1, and the number of elements And 5 in each the group to which the resolving potentials are output, the digit to be converted is equal to 1), and the second inputs of the elements of the AND 5 groups are connected to the clock outputs of the distributor 11 pulses. In order to carry out the multiplication operation, the trigger 4 is set to the initial state, in which the permissive potential at the output 13 of the reverse trigger 4 is excited. This Potential permits counter 3 to operate in add mode, and counter 2 in subtraction mode. The operation of the multiplication begins with the application of a clock frequency to the input 23 of the distributor 11 of a pulse. owls The first impulse from the output 15 of the distributor 11 is determined by the elements and 29 transfer drivers 17, except for the high-order transfer drivers 17 and the elements AND 9. At the initial moment, the elements 29 are locked with prohibition potentials of D-flip-flops 27, and the latter with inhibiting potentials corresponding outputs 16 of the shift distributor 10, to the second control input of which a signal of a logical unit is given. The same first pulse from the distributor 11 pulses through the inverter 12 (delayed for the duration of the pulse itself) is fed to the first clock input of the distributor 10 shift, in which the first of the buses 16 corresponds to one of the counters 2 digits multiplier, the value of the recorded digit is different from zero, appears jio tencial. The latter unlocks the AND 25 and AND-OR 26 elements associated with this bus, the switch 7 and the corresponding AND 9 element. The inverted first pulse of the distributor 11 from the output of the NO 12 element simultaneously polls the AND 29 element of the 2nd transfer former 17. In the initial state, the transfer unit of the imaging unit 17 records the transfer unit in the O-flip-flop 27, while the initial state of the D-triggers 27 of all the other transfer generators does not contain the unit of transfer. The 2nth transfer driver polled by the inverted first pulse does not read the transfer unit recorded in D-flip-flop 27, since the transfer transfer valve of this circuit is closed due to the presence of the inhibitory potential at the dividing input 21 of the device. The second, third, and so on. The first pulses of the distributor 11 are fed successively to the inputs of the corresponding elements of AND 5 groups. The outputs of the elements OR 6 are the outputs of a series of pulses equal in the number of pulses to the numbers of the corresponding multiplicative bits. These pulses through the elements AND 25 and -OR 26 of the commutator 7 arrive through the elements OR 8 at the counting inputs

the corresponding bits of the counter 3. After the B clock pulses, one cycle of the distributor 11 pulses ends, and the multiplicand is written once to the counter 3. The next first pulse from the output 15 of the distributor 11 polls the transfer drivers 17 and, through the open element I 9, subtracts one from i- pro bit multiplier. In each successive cycle, the value of the multiplicand is added to the contents of counter 3, and one is subtracted from the i-th bit of counter 2. In the case of the occurrence of 3 units of the transfer signal to the high bit or the through transfer signal in the addition process, each pulse from the output 15 of the distributor 11 is recorded through the transfer outputs of the transfer conditioners 17 and the elements OR 8 to the corresponding bits of the counter 3. Thereafter as the contents of the counter of counter 2 multiplier, which is multiplied, after the next subtraction of the unit becomes equal to zero, at the output of the element 18, decoding the code of the i-th counter of counter 2, a signal appears th switching Perg vym inverted pulse (output NOT element 12) of the first clock input, the distributor 10 changes. The output bus 16 of the distributor 10 shifts connects a valve 9 of a lower order, the contents of which are different from zero, and a friend connected to the bus 16, a group of elements AND 25 and AND-26 of switch 7, i.e. there is a shift of the multiplicand. The multiply operation ends when the values of all the bits of counter 2 become equal to zero, and on the shift distributor bus 24 a signal appears to indicate the end of the operation. .

The operation of deciding the numbers in the proposed device is carried out by the division method with the recovery of the negative balance. The operation of the device in the division mode is as follows. The dividend is recorded in the counter 3, and the divisor is recorded in the converter 1, and the low bit of the dividend is written to the low bit of the counter 3. The reverse trigger 4 is reset to which the counter 3 is ready for operation in addition mode, and the counter 2 is in subtraction mode. In the dividing mode, in the presence of a unit signal at the input 21, the shift distributor 10 is switched over the second clock input by a signal from the output 14 of the counter 4 of the reverse. The signal at input 21 also allows polling of the O flip-flop 27 of the 2-nd transfer driver 17, carried out from the output of the HE element 12 with each first impulse of the distributor 11. The division operation starts with the clock frequency applied to the device input 23. As in the multiplication, the first pulse from the output 15 of distribution 11 does not affect the state of the reversible counters 2 and 3. This pulse, coming from the output of the element HE 12, polls the 2nth transfer driver 17, reads the recorded in the 0-flip-flop 27

Former unit of transfer and throws on the counting input trigger 4 reverse. A change in the potentials at the outputs of the latter permits the operation of counter 3 in the subtraction mode, counter 2 in the addition mode, and switches the distributor 10 shifts. The signal from the output 16 of the distributor 10 resolves the operation of the element I 9 of the highest partial discharge and connects the switch group 7 connected to the output 16 of the distributor G 10 of the elements AND 25 and AND-OR 26 of the switch 7. After the first B-1, the pulses delivered by the distributor 11 to the elements And 5, groups, a one-time subtraction of the divider from the contents of the high bits of the counter 3 is performed. The first pulse of the next cycle of the pulse distributor 11 is written to the highest bit.

 counter 2 and carry out interdigit transfers in counter 3. The same inverted pulse (from the output of the element NO 12), interrogates the O-flip-flop 27 of the 2nd transducer, in the case of a positive

 remainder (absence of transfer unit in D-flip-flop 27) during the second cycle of the distributor .11 the divider value is again subtracted from the contents of the higher bits of the divider, and the first pulse of the third cycle of the distributor 11 second unit is written to the high bit of counter 2. Subtraction is performed before the negative bits of counter 2 are formed in the higher bits. In this case, a unit is recorded in the D flip-flop 27 of the 2nth transfer driver 17. The first impulse of the next cycle, the unit adds Q sec to the contents of the highest bit of the quotient counter, and flies the trigger 4 reverses with the same inverted impulse. The entire cycle of work started. Distributor 11 counters 3 work on addition and in them

 the remainder of the previous cycle is restored, and a transfer unit is recorded in the O-trigger 27 of the 2nth transfer generator. The first pulse of the next cycle additionally recorded units are subtracted from the high bit of counter 2, and the transfer unit from the 2nth generator, 17, is read with the same inverted pulse. transfer and reuse

5 flip-flop 4, reversing the operation of counters 2 and 3 and switching the valve 10 shifts to the next position. The shear distributor allows the valve 9 to operate at a lower partial discharge and connects another group of valves 7 of the shear matrix of the divider. Thus, in the started cycle, the pulses from the OR 6 elements arrive through the switch 7 to the lower bits of counters 3. Following the cycles until a negative balance is formed, counters 3 work on subtraction, and counters 2 on addition. The division operation is carried out until the flip-flop of 4 reverses occurs when a negative balance is formed in the lower digits of the counter 3 of the dividend, and it is restored to a positive balance or zero. Then, at exit 23, an indication of the end of the operation appears.

The speed of the multiplying-dividing device is determined by the clock frequency F. The following period of the clock pulses

where T, is the maximum duration of transient processes in the discharge of counter 3 (2),

Tgi- duration of transients when switching the shift distributor. The pulse duration at the output of the first distributor channel 11 pulses must be at least T.

Shaper 17 transfer works as follows.

In multiplication mode (addition mode for counter 3) output resolution 13 is applied to the potential of element 31. Another input of element 31 is connected to the decryption output B-1 of this counter 3. When digit B-1 is recorded in the discharge of counter 3 , at the output of the element And 20 of the code B-1 decoding, a high potential is necessarily present. When the discharge of the counter 3 overflows, the voltage drop from high to low along the element circuit AND 31, elements OR 32 and 33, and element NO 36 sets the O-flip-flop 27 to one state. The resolving potential from the unit output of the trigger 27 through the second input of the element OR 32 is fed to the first input of the element AND 29. A polling pulse arriving at the polling input of the former generates a transfer unit to the next bit using the element AND 29. The falling edge of the polling pulse D-trigger 27 returns to its original state. In the case of the presence of a unit from the previous bit in the given digit and the digit B-1 recorded in this bit, the unit of transfer through the second input of the element OR 35, through the element AND 28, allowed by the high potential from the output of the element 20 And the decoding of the code B-1 of this bit, is fed to the first input of the element AND 29 of the transfer of the transfer of the bit. The unit of transfer from the given bit to the next one and the unit of transfer from the previous bit to the present bit are formed by a polling pulse. In this case, an additional unit is written to the O-flip-flop 27 of this bit.

to transfer to the next bit, which is erased at the end of the polling pulse (its back edge). Organizing the recording of the through transfer unit to the next bit when

The 15 digits recorded in the previous digits of B-1 are made analogously on the first input of the element OR 35.

In the division mode (subtraction mode for counter 3), the resolving potential is supplied from the subtractor input of the shaper to the input of the element 30, the other input of which is connected to the output of the element 9 of the zero code decryption of the state of the corresponding counter 3. The circuit works similarly to 25 counter 3, only the counter overflow signal of the counter is the potential drop from high to low when the counter discharge state S goes from

0 recorded number About to figure B-1. The third input element And 29 2n-shaper connected to the control input shaper. The shear distributor operates as follows.

five

The initial state of all trigger triggers is zero. In multiplication mode, the resolving signal is present on bus 22. This signal resolves the operation of AND 39 elements of the second group and AND 42 (clock

0 are every first inverted pulse of the distributor 11). The first trigger is ready for switching with the first tau pulse. Switching each trigger to follow

Bit 5 is resolved by the corresponding decoding input of the zero distributor connected to the decoder output zero of the corresponding counter 2, and the output of the pre-discharge bit I.39. Thus, switching the trigger of each bit depends on the contents of all previous bits of counter 2. Switching one (or several

5 triggers) occurs when the contents of the previous bit (or the previous bits) of the counter 3 is zero. This eliminates the multiplication of the multiplicand by the zero values of the multiplier. Decrypt-

0 signals at the outputs of the distributor control for the i-th bit are performed by a group of two-input elements AND 40 according to the equation

Claims (2)

V O -. (N 1 Jii-n. In the dividing mode of the device, the permissive signal is present at the first control input of the resolver. I The latter allow the operation of the elements AND 38 of the first group and the element AND 4 3. In this mode, the triggers change From the pulses arriving at the second clock input of the distributor sequentially, not excluding intermediate states. Consequently, the connection of the AND 9 elements and the control inputs of the splitter switch (multiplicative) is carried out sequentially from the higher bits to the younger ones. Due to the additional hardware costs, the changes made in the known device allow to significantly increase the speed of operations by reducing the time required to transfer the transfer and eliminating the multiplication cycles by the zero digits of the multiplier. Formula 1. A device for multiplying and dividing a series-parallel action containing conversion repeater of the multiplier (divisor) digits into a unit code, reversible counters of digits of the multiplier (private). reversible counters of digits of the product (divisible), trigger of the reverse, n groups (n-width of operands) of elements AND, n of elements OR, switch, (2n-2) elements OR of countable signals, n of elements AND, shift distributor, pulse distributor and element NOT, with a single output of the reverse trigger connected to the subtraction inputs of reversible counters of digits of the multiplier (private) and inputs of addition of reversible counters of digits of the product (divisible), zero output of the reverse trigger is connected to the inputs of the addition of reversible counters of digits of the multiplier (private) and subtraction inputs of reversible counters p product (divisible), the counting input of each reversible digit counter of the multiplier (quotient) is connected to the output of the corresponding element I, the first input of each of which is connected to the corresponding control output of the shift distributor, the second input - with the output of the first pulse of the pulse distributor cycle, the first the inputs of the elements And the i-th group (i. one , . , ./ |) are connected to the corresponding outputs of the i-th group of converters of the multiplicand (divisor) into a single code, the second inputs of kx elements AND of each group (k 1, ..., 8, where B is the base of the number system). with the corresponding synchronization outputs of the pulse distributor, the outputs of the elements of the i-th group are connected to the inputs of the i-ro element OR whose output is connected to the corresponding information input of the switch, the control inputs of the switch are connected to the corresponding outputs of the control of the shift distributor, the first output The switch d is connected to the counting input of the first counter of the digits of the (divisible) digit, the switch outputs je (j 2, ..., (2n-l)) are connected respectively to the first inputs (j -1) -X of the OR elements of the counting signals whose outputs connected to the counting inputs jx of the digit (divisible) digit counters, characterized in that, in order to improve speed, transfer drivers, AND code decryption elements of the reversible counter counters are additionally introduced, and the output pulse of the first pulse of the pulse distributor En with element input NOT, element output is NOT connected to the first clock input of the shift distributor and the polling input of the transfer generator, the second clock input of the shift distributor is connected to the zero output of the reverse trigger, zero outputs of the i-th reverse counters of multipliers (private) are connected to the outputs elements And decoding the code of zero reversible counters of digits of the multiplier (quotient), the outputs of which are connected to the corresponding inputs of the decoding of the zero code of the shear distributor, the outputs of the elements AND decoding of the code well / 1 and elements And decoding of code B-1 of t-th reversible counters of digits of the product (divisible) (, ..., 2n) are connected to the corresponding inputs of decoding of code zero and decoding of code B-1 of t-th transfer formers, outputs of transfer (jl) -x transfer drivers are connected to the second inputs of the corresponding OR elements, the transfer output of the (2п-1) -th transfer generator is connected to the counting input of the 2nth product (divide) digit counter, the transfer output of the 2nth transfer generator is connected to the counting trigger input reverse, first and second in The through transfer ports of the 2nth transfer formers (... 2p) are connected to the corresponding outputs (2-1) of the transfer formers, the control input of the 2nth transfer generator is connected to the first control input of the shift distributor and is a division input of the device, The second control input of the distributor input is the input of the multiplying device, the pulse input of the pulse distributor is the clock input of the device, the output of the end of the operation of the shift distributor is the corresponding output of the device, direct and inverse The th output of the reverse trigger is connected to the addition and subtraction inputs of the transfer formers respectively, the bit outputs of the th reverse reversible counters of the output (divisible) are connected to the inputs of the corresponding two elements AND decryption of the zero code and the corresponding elements AND decryption of the B-1 2 code. A device according to claim 1, distinguished by the fact that each transfer maker contains a transfer D-trigger, four AND elements, four OR elements and an NOT element, and the output of the first AND element is connected to the first input of the first IL element and is the first output of end-to-end transfer of the transfer former, the unit output of the D-flip-flop is connected to the second input of the first IL element and is the second output of end-to-end transfer of the transfer former, the output of the first OR member is connected to the first input of the second AND member, respectively, the polling input and the control input of the transfer generator, the output of the second element AND is the transfer output of the transfer generator and connected to the first input of the second OR element, the output of which the input element is NOT, the element output is NOT connected to the synchronization input of the 0-flip-flop, the zero output of which is connected to its information input, the first inputs of the third and fourth elements of AND are respectively the subtractor and addition inputs of the transfer former, the second inputs are the inputs of the zero code decryption and decoding the code B-1 driver, the outputs of the third. and the fourth AND elements are connected to the inputs of the third OR element, the first and second inputs of the fourth OR element are respectively the first and second end-to-end transfer inputs of the former, the output of the third OR element is connected to the first input of the first AND element and the second input of the second OR element, output the fourth element OR is connected to the second input of the first element I. 3. The device according to claim 1 / wherein the shift distributor contains a group of elements OR, three groups of elements AND, element OR, two elements AND and n + 1 D-tr ggerov, wherein first inputs of first and second AND gates are respectively first and second clock inputs of the distributor elements and outputs connected to the inputs of the OR gate, whose output is connected to inputs of a synchronization O-flops, flip-flops unit outputs are connected to first inputs of corresponding. the first elements of the first group, the second inputs of which are connected to the second input of the second element AND and are the first control {input of the distributor, the outputs of the -th elements AND of the first group are connected respectively to the first inputs of the elements OR of the group, the outputs –yY. elements OR groups are connected respectively to information inputs (th D-flip-flops (tf 2, ... n + i). the first inputs of the i-th elements of the second group are connected to the second input of the first AND element and are the second control input of the distributor shifts, the second inputs - with the corresponding inputs of the decoding of the zero code of the shift distributor, the outputs - with the second inputs of the corresponding OR elements of the group, the outputs (the p-th elements of the second group (Ts 1, ... n-1) are connected respectively to the third inputs ( Wed + 1) -th elements And the second group, the first in the moves of the i-th elements of the third group are connected to the unit outputs of the corresponding O-flip-flops, and the second input elements are connected to the zero outputs vCp + 1) -X -O-flip-flops, the zero output of the first D-flip-flop is connected to the second input The nth element of the third group, the outputs of the elements of the third group are the control outputs of the shift distributors, the output (n +)) of the D-flip-flop is the output of the end of the shift distributor operation. Sources of information taken into account in the examination 1. Copyright certificates USSR № 190658, cl. G 06 F 7/52, 1966. 2. USSR author's certificate number 217718, cl. G 06 F 7/08, 1965 (prototype), U P 0 7J /five gz / tf r / f / ff /five . five / 7 t n "kz 25 5 B Sb to i- G-, le uiiB 6 It and Id f tfjfffff