SU815884A1

SU815884A1 - Frequency doubler

Info

Publication number: SU815884A1
Application number: SU792780640A
Authority: SU
Inventors: Василий Степанович Никонов; Геннадий Иосифович Парфенов; Николай Андреевич Грачев
Priority date: 1979-06-13
Filing date: 1979-06-13
Publication date: 1981-03-23

Description

(54) УДВОИТЕЛЬ ЧАСТОТЫ(54) FREQUENCY ALTERNATOR

II

Изобретение относитс к импульсной технике и может быть использовано в измерительных устройствах.The invention relates to a pulse technique and can be used in measuring devices.

Известно устройство умножени частоты , Содержащее двухполупериодный выпр митель , компараторы, делители напр жени 1A frequency multiplying device containing a full-wave rectifier, comparators, voltage dividers 1 is known.

Однако такое устройство имеет низкую точность умножени из-за зависимости точности делени от амплитуды сигнала.However, such a device has low multiplication accuracy due to the dependence of the division accuracy on the amplitude of the signal.

Наиболее близким техническим решением к предлагаемому вл етс удвоитель частоты , содержаш.ий генератор опорной частоты , делитель частоты, реверсивный счетчИк , элемент И, элемент ИЛИ 2.The closest technical solution to the proposed is a frequency doubler, containing a reference frequency generator, frequency divider, reversible counter, AND element, OR element 2.

Недостатком устройства вл етс низка точность работы.The disadvantage of the device is low accuracy.

Цель изобретени - повышение точности удвоени .The purpose of the invention is to improve the accuracy of doubling.

Поставленна цель достигаетс тем, что в удвоитель частоты, содержаший генератор опорной частоты, делитель частоты, первый реверсивный счетчик импульсов, элемент И, элемент ИЛИ, введены второй реверсивный счетчик импульсов, два дешифратора , элемент НЕ и второй, третий и четвертый элементы И, причем выход генератора опорной частоты соединен с первыми входамл первого и второго элементов И и со входом делител частоты, выход которого соединен с первыми входами третьего и четвертого элементов И, вторые входы которых и вход элемента НЕ подключены ко вхо-. ду устройства, а выход элемента НЕ соединен со вторыми входами первого и четвертого элементов И, при этом выходы первого и третьего элементов И соединены соответственно с вычитаюшим и суммируюшим входами первого реверсивного счетчика импульсов , выход которого соединен со входом первого дешифратора, а выходы второго и четвертого элементов И соединены соответственно с вычитающим и суммируюшим входами второго реверсивного счетчика импульсов , выход которого соединен со входом второго дешифратора, выход первого дешифратора соединен с третьим входом первого элемента И и первым входом элемента ИЛИ,The goal is achieved by the fact that a frequency doubler containing a reference frequency generator, a frequency divider, a first reversible pulse counter, AND element, OR element, is entered into a second reversible pulse counter, two decoders, a NOT element, and second, third and fourth elements AND the output of the reference frequency generator is connected to the first inputs of the first and second And elements and to the input of a frequency divider, the output of which is connected to the first inputs of the third and fourth And elements, the second inputs of which and the input of the element are not connected to the inlet. device, and the output of the element is NOT connected to the second inputs of the first and fourth elements AND, while the outputs of the first and third elements AND are connected respectively to the subtracting and summing inputs of the first reversible pulse counter, the output of which is connected to the input of the first decoder, and the outputs of the second and fourth elements And are connected respectively to the subtracting and summing inputs of the second reversible pulse counter, the output of which is connected to the input of the second decoder, the output of the first decoder connection n with the third input of the first element AND and the first input of the OR element,

а выход второго дешифратора соединен с третьим входом второго элемента И и вторым входом элемента ИЛИ.and the output of the second decoder is connected to the third input of the second element AND and the second input of the OR element.

Claims

The drawing shows a structural electrical circuit of the device. The device contains a reference frequency generator 1, a frequency divider 2, elements AND 3-6, element NOT 7, counters ", 9 pulses, reversible decoders 10 and 11, element OR 12. The device operates as follows. The input signal with frequency arrives at the input of the element NOT 7 and at the second inputs of the elements AND 3, 6. At the same time, the signal of the reference frequency of the generator 1 through the divider 2 is fed to the first inputs of the element; s And 3, 5. Thus, at the output of the element 3, is a signal with a frequency of two times less than the frequency of the reference oscillator 1, and therefore, for the duration of the positive period of the input signal, the reversing counter 8 sums a number of pulses. After the end of the positive half cycle of the input signal through the element HE 7 and the element AND 4, the negative half period of the input signal enables the operation of the reversible counter 8 for subtraction. And since the subtracting pulses from the reference generator 1 are twice the frequency of the pulses from the splitter 2 frequencies, the counter is released from the information for exactly half a half period, as soon as this signal occurs through the decoder 10 prohibits the submission of the subtracting pulses to the input of the reversing counter 8, through element 4. At the output of the decoder, 10 a pulse is formed equal to half the period. During the duration of the negative half-cycle of the signal, in addition, a similar filling of the second reversing counter 9 occurs. Its release occurs during the first half of the next positive half-cycle and at the same time, as in the first case, the output of the decoder 11 produces a pulse equal to the half-half-period duration. The pulses from the first decoder 10 and the second decoder 11 are formed on the element OR 12, the output of which produces a doubled signal frequency. The device allows frequency multiplication with great accuracy, since in this case there are no special requirements for the frequency stability of the reference oscillator and the frequency stability of the pulses to be multiplied. The invention doubler frequency, containing a reference frequency generator, a frequency divider, the first reversible pulse counter, the element AND, the element OR, characterized in that, in order to improve the doubling accuracy, the second reversible counter of pulses, two decoders, the element NOT, the second , the third and fourth elements And, and the output of the reference frequency generator is connected to the first inputs of the first and second elements And, and to the input of the frequency divider, the output of which is connected to the first inputs of the third and fourth elements And, The second inputs of which and the input of the element are NOT connected to the input of the device, and the output of the element is NOT connected to the second inputs of the first and fourth elements AND, while the outputs of the first and third elements AND are connected respectively to the subtracting and summing inputs of the first reversible pulse counter, the output of which is connected with the input of the first descrambler, and the outputs of the second and fourth elements of And are connected respectively to the subtractive and summing inputs of the second reversible pulse counter, the output of which is connected to the input of the second the first decoder is connected to the third input of the first element AND and the first input of the OR element, and the output of the second decoder is connected to the third input of the second element AND and the second input of the OR element. Sources of information taken into account in the examination of 1- USSR Copyright Certificate № 285987, cl. H 03 B 19/20, 07.02.69.

2. USSR author's certificate No. 542338, cl, H 03 K, 5/156, 28.01.76.