SU809547A1 - Digital-analogue converter - Google Patents

Description

(54) DIGITAL TRANSFORMER

The invention relates to computing and measuring technology and can be used in information-measuring systems and automatic control systems. Digital-to-analog converters (DACs) are known, which contain a current or voltage generator, switches and resistor arrays, working by the method of summing up binary-weighted standards 1. The drawback of the devices is the lack of means of health monitoring. Also known is a digital-to-analog converter containing a chain current divider, to the outputs of which are connected the switch outputs, the information input of one of which is connected to the output of the DC generator, the information inputs of the other current switches are connected to the outputs of the controlled current generators, and the control inputs connected to the outputs of the control unit; the output of the chain dividers is connected via a capacitor to the first input of the comparator, the second input of which is connected to the zero potential bus, and stroke - with the input of the phases of the sensing rectifier, the output of which is connected to the information input of the distributor, the control inputs of which are connected to the outputs of the control device, and the outputs - to the inputs of analogue storage devices whose outputs are connected to the inputs of controlled current generators 2. The disadvantage of the device is There is no possibility of detecting and visually observing gradual failures. The purpose of the invention is the detection and visual display of gradual failures. The goal is achieved by the fact that in the converter containing a chain current divider, to the outputs of which are connected the outputs of current switches, the information input of one of which is connected to the output of the DC generator, the information inputs of the other current switches are connected to the outputs of the controlled current generators. cadium inputs are connected to the outputs of the control device, the output of the chain current divider is connected via a capacitor to the first input of the comparator,

the second input of which is connected with the zero potential, and the output to the input of the phage-sensitive rectifier, the output of which is connected to the information input of the distributor, the control of which inputs are connected to the outputs of the control device, and the output - to the inputs of analog sniper memory whose outputs are connected to the inputs controllable current generators, a register, an indicator and a two-threshold element are entered, cara | Neni, whose input is connected to the output of a phase-sensitive rectifier, and the output is connected to the control input regis pa, data inputs of which are connected with the control-inputs of the distributor, and the outputs - to the inputs of the indicator.

The drawing shows the functional electrical circuit of the device.

In the device, the inputs of the discrete current divider 1 are connected to the outputs of the current switches 2, whose information inputs to the outputs of the controlled current generators 3 and the DC generator 4, and the control inputs to the outputs of the control device 5.

Inputs controlled generators. the current is connected to the outputs of the analog storage devices 6. The output of the chain divider 1 of the current through the capacitor 7 is connected to the input of the comparator 8, the second input of which is connected to the zero potential bus, and the output to the phase-sensitive rectifier 9. The output of the latter is connected to the information distributor input 10, the control inputs of which are with the outputs of the control device 5, and the outputs with the inputs of analog storage devices. The input of the two-threshold comparison element 11 is connected to the output of the phase-sensitive rectifier 9 and the output to the information input of the register 12, the control inputs of which are controlled by the inputs of the distributor, and the outputs with indicator 13.

The operation of the device is as follows.

The device operates in two modes - correction and conversion. Re) the correction consists of N cycles, where $ N is the width of the digital cyclic index, and each cycle consists of several (10-20J cycles,; each of which is divided into two half-cycles. In the correction cycle of each i-oro bit in the first half-cycle the corresponding clock at the output of the control unit generates a code containing the logical unit in the reference bit and in the first i bits, the keys controlling the bits lower than the currently adjusted bit. In the second half of the code, the code containing the unit is only in the adjustable bit de. on the distribution During the cycle, the code is continuously supplied with a code ensuring that it is switched in such a way that the output of the phase-sensitive rectifier is connected to the input of the analog I-bit storage device. The negative feedback closed circuit is a phase-sensitive rectifier - the analog storage device of the i-th discharge — controlled current generator — current switch of the 1st discharge. —the chain current divider tends, with a sufficiently large coefficient. of the comparator to the state at which the output pulsation ode chain current divider close to zero, i.e.

m (1)

,

Jc

where ji is the current value

post generator

Ij

- the value of the generator current is the lowest current in relation to the –th one;

KQ, KJ, HKJ - coefficients

transferring the corresponding current to the output of the divider, having the dimensionality of resistance;

Kyli

is the weight coefficient of the nth ratio.

In this case, with a larger deviation of the parameters of the corresponding current generator from the nominal, the control voltage at the output of the phase-sensitive rectifier 1. ™ bodies also deviates more from its nominal value. At the end of the correction cycle, the analog storage device is disconnected from the distributor by the phase-sensitive rectifier, and the corresponding control voltage is memorized.

In the first correction cycle, starting with the least significant bit, in accordance with expression (1) is set

(KoIo

In the second cycle, the current of the second discharge is corrected, as a result we get

 KoIotK l 2Kolo

In the third cycle, the current of the third discharge is corrected, as a result we get

 3l3 olo-il-i -i al7. 4Koio

etc. After N correction cycles for any -th bit of the D / A converter, the ratio

,

those. the weights of the transducer bits are proportional to the degree of two from the bit number, and therefore the linearity of the conversion characteristic is ensured from a voltage to a code with very significant deviations of the parameters of the components from the nominal values.

The trigger levels of the two-threshold comparison element are set near the limits of the voltage range allowed for controlling the current generator, and within this range.

If, when changing the parameters of the adjustable bit of the DAC, to compensate it, a control voltage is necessary / close to the limit of permissible stresses, i.e. depends on the nature; If the parameters change by the end of the correction cycle is greater than or lower than the lower thresholds of the two-threshold comparison element, then a signal appears at the output of this element, which is taken as a logical unit and is a sign of a cash failure. This signal is fed to the control input of the register K and is recorded in the reg; a code r that controls the distributor that uniquely corresponds to the number of the digit currently being corrected. This code is stored in a register and is displayed on the indicator to visually display the number of the bit whose parameters are close to the limit.

Claims (2)

1. Microelectronic encoding and decoding converters. Ed. Smolova V.B. L., Energie 1976. 2. Graben A.B. Designing analog integrated circuits. M., Energie, 1976.