SU798837A1 - Processor control device - Google Patents

Description

the logical zero of the device, whose startup input is connected to the inputs of the switchboard additions and the command address, entered the command packet register, packet command counter, packet command decoder, transition address switch, additional unpacking switch, second decoder; a team swarm, first and second additional adders, the information input of the command package register is connected to the device command input, the output of the command package register command length is connected to the information input of the command command counter, the start input of which is connected to the device word input, the output of the package command counter is connected with the first input of the decoder of the packet command, the second input of which is connected to the input of the operation code of the command packet register, the address output of which is connected to the information input of the switchboard the transition address, the control input of which is connected to the output of the command decoder of the packet, the output of the switch of the transition address is connected to the output of the address and type of the device transition, the group of information inputs of the additional unpacking switch is connected to the second bit outputs of the buffer registers of the group command, the control input of the additional unpacking switch connected to the output of the first additional adder, the first and second inputs of which are connected, respectively, with the address output and the input command length device, the output of the additional unpacking switch is connected to the input of the decoder of the second command, the first and second outputs of which are connected respectively to the control inputs of the switchboards and command addresses, the third output of the decoder of the second command is connected to the first input of the second additional adder, the second input of which is connected to the input of the device command length, and the output of the second additional adder of the coupling with the additional information input of the switchboard of additives.

Introduction of the command packet register, command counter of the command decoder packet. packet, the switch of the jump address allows to ensure the call of a new sequence of commands ahead of the execution of the jump command,

The introduction of an additional unpacking switch, a second decoder, a first and a second additional adder allows detection and execution of a transition command in parallel with the decryption of the previous command, which saves time for reading and decoding the transition command.

The drawing shows a block diagram of the device.

The device contains buffer registers 1 commands, switch 2 decompression, switch 3 command addresses, switch 4 additives, adder 5, register 6, register command package 7, packet command counter 8, decoder 9 packet commands, switch 10 address switch, additional unpacking switch 11 decoder 12 second, additional adders 13 and 14.

The device works as follows.

The commands to be executed come to the outputs of the device through switch 2 from registers 1. Control of switch 2 is carried out

the current address of the command being executed (its first word number) stored in register 6.

When the program starts, the signal from the device inputs controls switches 3 and 4. The inputs of adder 5 receive the start address from the device inputs through switch 3 and the zero information through switch 4. From the outputs of adder 5, the start address goes to register 6. Possibility of its further changing It depends, first of all, on the result of checking whether the current command changes in

registers 1. To check the current

the address is issued from register 6 on

the outputs of the device. In the absence of a command, its call from memory is organized.

After decrypting the current command, its length from the device outputs

through the switch 4 enters the outputs of the adder 5, where it is added to the address of the initial word of this command arriving at the other inputs

adder 5, the address of the command following the current, formed at the outputs of adder 13, controls the switch 11, which allocates the following command from the outputs of registers 1

and delivers it to a decoder 12 that recognizes transition instructions.

If the command at the inputs of the decoder 12 is not a transition command, then the outputs of the adder 5 receive information from the register 6 and from the inputs

devices.

If the command at the inputs of the decoder 12 is a transition command, and this one according to which the decision is made to continue calculations on the new branch, then the inputs 5 receive zero information through the switch 4 and information from the device inputs through the switch 3.

Claims (2)

If the command at the inputs of the decoder 12 is a jump command. moreover, according to which a decision is made to continue calculations on the old branch of the program, the inputs from adder 5 receive information from register 6 and adder 14. Adder 14 forms at the outputs the sum of the current command coming from the device inputs and the length of the next command coming from the outputs of the decoder 12. If there is a free register in the command buffer, it also receives another packet of commands from the device & register 7. Counter 8 contains the number of the first word of the first command of the packet, which upon initial start-up, as well as changing the order of the commands, enters it from the device inputs. From the outputs of register 7, the code groups of the command lengths from all the words of the packet come to the inputs of the counters. Counter 8 determines the numbers of the original words of all the commands in the current packet and the first command in the next packet, thus being prepared to work on the next packet. The inputs of the decoder 9 with the outputs of the register 7 receives the group of bits containing the operation code from each word of the packet. The decoder 9 in the presence of the code group of the transition operation in any words of the packet matches the numbers of these words with the numbers of the initial words of the commands of the packet coming from the counter. If any numbers coincided, this means that the command of the transition begins with this word ( it is assumed that the opcode is in the first word of the command). The word number of the packet in which the transition command is found (the first command itself, if there are several of them in the packet) from the outputs of the decoder 9 controls the switch 10. Through the switch 10, the device outputs receive the address and type information contained in the command. If this batch of commands is not detected, by the following timestamp, if there are free buffer registers 1 to one of them, the next batch of commands is received in register 7, the contents of counter 8 are updated and the process is repeated. If a transition command is detected in this packet, instruction paging is organized based on information obtained from the device outputs. The device allows you to make the transition in the program without time consuming, since it does not take time to wait for a new command sequence. The performance of the Jutva arrangement is greater, the deeper the combination of operations of this computer and the greater the transitions among the executed commands. Formula of the processor control unit containing a group of buffer command registers whose information inputs are connected to the input of device commands, the first group outputs of the buffer registers are connected to the group of information inputs of the unpacking switch, the output of which is the output of the device commands, the control input of the unpacking switch is connected to the register CiBfcejOflOM and esting output device, an information register soedinens .The inputs of the adder output, a first input coupled to an output switch command address, a second input connected with the output of the adder additives switch address input switch command address. is the address input of the device, the information inputs of the switch are the command address connected to the register output, the input of the command length and the zero information of the additional switch are connected respectively to the command length and logical zero of the device, the start input of which is connected to the inputs of the switch of the additional switches and the command address, characterized in that, in order to achieve speed, a command packet register, a packet command counter, a packet command decoder, a jump address switch, an additional comm unpacking-decoder second command, the first and second additional adders, and the information input of the instruction package register is connected to the device command input, the output of the command package register command length is connected to the information input of the command command counter, the start input of which is connected to the device word number input, the output of a packet command counter is connected to the first input of the command decoder of the packet, the second input of which is connected to the input of the operation code of the register of the command packet, the address output of which is connected to the input The switch input of the switch addresses the transition, the control input of which is connected to the output of the decoder packet commands, the switch address switch output is connected to the output of the device’s address and type of transition, the group of information inputs of the additional unpacking switch is connected to the second bits of the group command registers, the control input of the additional unpacking switch is connected to the output of the first additional adder, the first and second inputs of which are connected respectively to the address input output device instruction length, additional switch output unpacking is connected to the input of the second command decoder, the first and second outputs of which are connected, respectively, to the control inputs of the switchboards and command address, the third output of the second command decoder is connected to the first input of the second additional adder, the second input of which is connected to the device command length input , and the output of the second additional adder is connected to the additional information input of the additive switchboard. Sources of information taken into account in the examination I.R.N.JfetJettpTfte MU-S pipef-ine computer j.,. fS Ni 2. EC-1050 computer. Ed., A.M. Larionova, M., Statistics, 1976 (prototype).