SU798812A2

SU798812A2 - Digital null device

Info

Publication number: SU798812A2
Application number: SU782681285A
Authority: SU
Inventors: Фикрет Микаилович Аллахвердов; Назим Габиб Оглы Бабаев; Юрий Владимирович Каллиников; Кямиль Агабаба Оглы Гасанов
Priority date: 1978-11-09
Filing date: 1978-11-09
Publication date: 1981-01-23

Description

(54) ЦИФРОВОЙ Н Изобретение относитс к автоматик и вычислительной технике и может быт использовано дл определени момента совпадени частот дл последовательностей импульсов в быстродействующих системах управлени и измерени . По основному авт. св. № 335685 известен цифровой нуль-орган, содержащий преобразователь код-временной интервал, образованный вычитающим счетчиком, генератором импульсов, трем лини ми задержки, триггером, вентилем, схемой ИЛИ и вентил ми ввода кода в вычитающий счетчик, формирователь импульсов, схему совпадени и измеритель периода заданной частоты, образованной счетчиком импульсов, запоминающим регистром, вентил ми ввода кода в регистр, схемой запрета и двум лини ми задержки , источник импульсов текущей частоты подключен к управл ющему входу преобразовател и через последовательно соединенные первую, вторую и третью, линии задержки - к первому входу схемы совпадени , к второму входу которой подсоединен через формирователь импульсов выход преобразовател , входы вычитающего счетчика которого соединены через вентили РГАН -il 2 | и :;;;и: чЛЧ ввода кода в вычитаюсдай счетчик с выходами запоминающего регистра, входами подключенного через вентили ввода кода в регистр к выходам счетчика импульсов, счетный вход которого соединен с выходом генератора импульсов , сбросовый вход через последовательно включенные четвертую и п тую линии задержки - к выходу источника импульсов заданной частоты, соединенному с сбросовым входом запоминающего регистра через схему запрета, управл ющий вход которой подключен к концу второй линии задержки , причем управл емые входы вентилей кода в регистр св заны с концом четвертой линии задержки 1. Недостатком этого устройства вл етс низка точность в широком диапазоне частот. Оно позвол ет полу чить высокую точность только дл медленно и монотонно измен ющейс текущей частоты, когда приращение периода незначительно. Дл учета динамики примен ют формирователь импульсов , расшир ющий один из сравниваемых по времени«мпульсов, величину длительности которого необходимо увеличить с ростом скорости изменени периода текущей частоты.(54) DIGITAL N The invention relates to automation and computer technology and can be used to determine the instant at which frequencies coincide for sequences of pulses in high-speed control and measurement systems. According to the main author. St. No. 335685 is a digital null organ that contains a code-time converter, formed by a subtracting counter, a pulse generator, three delay lines, a trigger, a gate, an OR circuit, and code entry gates to the subtracting counter, pulse driver, coincidence circuit, and period meter a predetermined frequency formed by a pulse counter, a storage register, code entry valves into the register, a inhibitor circuit and two delay lines, the source of current frequency pulses is connected to a control input of the transform ate through the serially connected first, second and third lines of delay - to the first input coincidence circuit to a second input of which is connected via a pulse shaper output converter, the inputs of the subtracter counter which is connected via valves RGANI -il 2 | and: ;;; and: hLCH enter the code into the subtraction counter with the outputs of the memory register, the inputs connected through the code input gates to the outputs of the pulse counter, the counting input of which is connected to the output of the pulse generator, the fault input through the fourth and fifth lines connected in series delays - to the output of the source of pulses of a given frequency, connected to the fault input of the memory register through a prohibition circuit, the control input of which is connected to the end of the second delay line, and the controlled inputs of the gates to The signals to the register are associated with the end of the fourth delay line 1. The disadvantage of this device is low accuracy over a wide frequency range. It allows high accuracy only for a slowly and monotonously changing current frequency when the period increment is insignificant. To take into account the dynamics, a pulse shaper is used, which expands one of the time-comparable м pulses, the duration of which must be increased with an increase in the rate of change of the period of the current frequency.

что снижает точность работы устройства . Особенно плохие результаты получаютс дл быстроизмен ющегос текущего сигнала в нижней части диапазона изменени .which reduces the accuracy of the device. Especially poor results are obtained for a rapidly changing current signal in the lower part of the range of variation.

Цель изобретени - увеличение точности в широком диапазоне частот..The purpose of the invention is to increase the accuracy in a wide frequency range.

Поставленна цель достигаетс тем, что в цифровой нуль-орган введены умножители частоты, делители частоты, счетчики, сумматор частот, узлы вычитани частот, узлы перезаписи, управл егИе делители частоты, причем выход генератора импульсов соединен с первызчи входами первого, второго и третьего управл емых делителейThe goal is achieved by introducing frequency multipliers, frequency dividers, counters, frequency adder, frequency subtractors, rewriting nodes, control frequency dividers into the digital null organ, the output of the pulse generator connected to the primary inputs of the first, second, and third controlled dividers

первымичастоты ,first frequency

входами первого, второго и третьего множителей частоты и с входом первого делител частоты, выход которого подключен к информационному входу счетчика, выходы которого соединены с входами первого узла перезаписи , выходы которого подключены к вторым входам первого, четвертого и п того управл емых делителей частоты , первый выход первого управл емого делител частоты соединен с входами второго узла перезаписи, выходы которого подключены к второму входу третьего управл емого делител частоты, первый выход которого соединен с входами третьего узла перезаписи , выходы которого подключены к вторим входам второго управл емого делител частоты, первый выход которого соединен с первым входом первого узла вычитани частот, выход которого подключен к первому входу шестого управл емого делител частоты, выход которого соединен с первым входом второго узла вычитани частот, выход которого подключен к первому входу п того управл емого делител частоты, выход которого соединен с вторым входом первого умножител частоты, выход которого подключен ко второму Bxoijy второго умножител частоты, выход которого соединен с первым входом сумматора, частот, выход которого подключен к первому входу устроства , выход второго узла перезаписи с|рединен с вторым входом шестого управл емого делител частоты, второй выход первого управл емого делител частоты соединен с вторым входом сумматора частот с первым входом третьего узла вычитани частот , первый выход которого подключен к третьему входу сумматора частот , а второй выход - к первому вхо:ДУ четвертого управл емого делител частоты и через второй делитель частоты к четвертому входу сумматора частот, второй выход третьего управл емого делител частоты соединен сinputs of the first, second and third frequency factors and with the input of the first frequency divider, the output of which is connected to the information input of the counter, the outputs of which are connected to the inputs of the first rewriting node, the outputs of which are connected to the second inputs of the first, fourth and fifth controlled frequency dividers, the first the output of the first controlled frequency divider is connected to the inputs of the second rewriting node, the outputs of which are connected to the second input of the third controlled frequency divider, the first output of which is connected to the inputs a recycle node whose outputs are connected to the second inputs of the second controlled frequency divider, the first output of which is connected to the first input of the first frequency subtracting node, the output of which is connected to the first input of the sixth controlled frequency divider, the output of which is connected to the first input of the second frequency subtraction node The output of which is connected to the first input of the fifth controlled frequency divider, the output of which is connected to the second input of the first frequency multiplier, the output of which is connected to the second Bxoijy of the second intelligently the resident of the frequency, the output of which is connected to the first input of the adder, the frequencies, the output of which is connected to the first input of the device, the output of the second rewriting node from | is connected to the second input of the sixth controlled frequency divider, the second output of the first controlled frequency divider is connected to the second input of the frequency adder with the first input of the third subtraction node, the first output of which is connected to the third input of the frequency adder, and the second output to the first input: the remote control of the fourth controlled frequency divider and through the second frequency divider s to the fourth input of the frequency adder, the second output of the third controlled frequency divider is connected to

вторыми входами nepBOio и третьего узлов вычитани частот, первый выход четвертого управл емого делител частоты подключен к второму входу второго узла вычитани частот и к второму входу третьего умножител частоты, выход которого соединен с п тым входом сумматора частот, выход первого делител частоты к второму входу устройства. Причем кажды из управл емых делителей частоты состоит из счетчика, регистра и узл перезаписи, первый вход узла соединен с информационным входом счетчика , выход которого подключен к входу управле«и узла перезаписи и к второму выходу узла, второй вход узла соединен с входом регистра, выход которого подключен к первому выходу узла и к входу узла перезаписи , выходы которого соединены с входами счетчика.the second inputs of the nepBOio and the third subtraction frequency node, the first output of the fourth controlled frequency divider is connected to the second input of the second frequency subtracting node and to the second input of the third frequency multiplier, the output of which is connected to the fifth input of the frequency adder, the output of the first frequency divider to the second input of the device . Moreover, each of the controlled frequency dividers consists of a counter, a register and a rewriting node, the first input of the node is connected to the information input of the counter, the output of which is connected to the control input and the rewriting node and to the second output of the node, the second input of the node which is connected to the first output of the node and to the input of the rewriting node, the outputs of which are connected to the inputs of the counter.

На чертеже представлена блок-схема устройства.The drawing shows the block diagram of the device.

Устройство содержит преобразователь 1 код-интервал, состо щий из вычитающего счетчика 2, генератора 3 импульсов, линий 4-6 задержки, триггера 7, вентил 8, схемы ИЛИ 9 и вентилей 10 ввода кода в вычитающий счетчик, формирователь 11 импульсов , схему 12 совпадени , измеритель 13 периода заданной частоты, состо щий из счетчика 14 импульсов, запоминающего регистра 15, вентилейThe device contains a code-interval converter 1 consisting of subtractive counter 2, pulse generator 3, delay lines 4-6, trigger 7, valve 8, circuit OR 9, and code input valves 10 in the subtracting counter, pulse generator 11, coincidence circuit 12 , the meter 13 period of a given frequency, consisting of a counter 14 pulses, memory register 15, gates

16ввода кода в регистр 15, схемы16 input code in the register 15 schemes

17запрета и линий 18 и 19 задержки умножители 20-22 частоты, делитель 23 частоты, счетчик 24, сумматор 25 частот, узлы 26-28 вычитани частот делитель 29 частоты, узлы 30-32 перзаписи , узел 33 перезаписи, управл мые делители 34-39 частоты, кгикдай17 banned and delay lines 18 and 19 multipliers 20-22 frequencies, frequency divider 23, counter 24, frequency adder 25, frequency subtractors 26-28 frequency divider 29, recording nodes 30-32, rewriting node 33, control dividers 34-39 frequencies, kgikday

из которьк состоит из счетчика 40,, узла,33 перезаписи и регистра 41, шины 42-48 управлени , входную шииу 49, выходную шину 50.It consists of a counter 40, a node, 33 rewrites and a register 41, control buses 42-48, input bus 49, output bus 50.

Устройство работает следующим образом .The device works as follows.

Из каждого импульса последовательности сигнала текущей частоты т(t) формируютс на выходах 42-48 сигналы, управл ющие последовательностью работы блоков устройства. С выхода генератора 3 импульсы опорной частоты ff( поступают на входы счетчиков 40 управл е1«1х делителей 34, 35 и 37 частоты, на входы делител 23 частоты , умножителей 20-22 частоты и через веитиль 8 иа входы вычитающего счетчика 2. В делитепе 23 частоты опорна частота делитс на jiqcTOHHHbrfl коэффициент К, вл ющийс кЪэффициен60 том умножени устройства. В управл емых делител х 34, 35 и 37 частоты опорна частота делитс на переменные коэффициенты, записываемые в виде параллельного кода в регистры 41From each pulse of the current frequency t (t) signal sequence, signals are generated at the outputs 42-48 that control the operation sequence of the device blocks. From the output of the generator 3, the pulses of the reference frequency ff (fed to the inputs of the counters 40 control e1 "1x dividers 34, 35 and 37 frequencies, to the inputs of the frequency divider 23, multipliers 20-22 frequencies and through the power 8 and inputs of the subtracting counter 2. In the split 23 frequency reference frequency is divided by jiqcTOHHHbrfl coefficient K, which is the coefficient of the device multiplication factor.In controlled dividers 34, 35 and 37, the frequency reference frequency is divided into variable coefficients, written as a parallel code in registers 41

Claims

65 after the end of each period of the current frequency. The pulses following the frequency Fg -j from the output of divider 23 are fed to the input of counter 24, where they are summed up in a time interval equal to the ending period of the current frequency and generated by applying to the control input 42 signals control after the arrival of each pulse of the current frequency. At the outputs of the counter 24 at the time of the survey, a code is generated that is proportional to the ending period of the current frequency. This code, before resetting the counter 24 through the rewriting node 30, on a signal at control 48, is written to control registers 41, frequency dividers 34, 36, and 39. Before zeroing the register 41 of the controlled frequency divider 34, the code contained therein, which is proportional to the previous (i-l) -OMy period T-j.-f, is overwritten via the rewriting unit 31 to the registers of the controlled frequency dividers 35 and 38. Before zeroing the register of the controlled divider, 35 is its frequency code, proportional to the (1-2) -th period. is rewritten by a signal at input 44 through rewriting node 32 to the register of a controlled frequency divider 37. Thus, after the end of the i-th period of the current frequency fr (t) in the registers of controlled dividers 34,35 and 39 frequencies, the K code is recorded. In the registers of controlled frequency dividers 35 38, the code is recorded, in the registers of the controlled frequency divider 37 - code Np | . At the outputs of the controlled dividers 34, 35, and 37 hours, respectively, frequencies of P (C) are formed ;. kfT-ct); ). ; F (t, -. 2) sfe kf-r (, j), i.e. increased frequencies in K pa corresponding to the instantaneous values of the current frequency in three adjacent periods T | , T - {- {and .. Pulses with FREQUENCY1 F (t;) and F (t; j from the outputs of the controlled frequency dividers 34 and 35 are fed to the inputs of the frequency subtraction node 26, at the information output of which a sequence of pulses is formed, The average frequency LG (ti) Fr () - F (t.) k & fj (t) is proportional to the increment of the current frequency during the 1st period. At the sign output of the frequency subtracting section 26, a signal sign of the increment sign Siq L Fy is formed ( t;), corresponding to the sign of the derivative of the current frequency in the i-th period. Accordingly, the pulses with frequencies gG - (t 1-) and F () from the outputs of the controllable divisors Frequency lines 35 and 37 are fed to the inputs of subtracting node 27, the output of which forms a sequence of pulses with an average frequency bF – r (t. kAf. (t)) proportional to the increment of the current frequency over time (il) - period. the frequency divider 36, the frequency AP (t) from the output of the frequency subtraction node 26 is divided by a factor N - - j. At the output of the controlled frequency divider 36, a sequence of pulses is formed with a frequency Gt (1, -) (- (t, -) is proportional to the average value of the first time derivative of the current frequency in the i-th period. In the controlled frequency divider 38 frequency), the output from node 27 of the frequency subtraction is divided by a factor. At the output of the controlled frequency divider 38, a sequence of pulses is formed with a frequency F; (t.i) 1 f; (t.,) Proportional to the average value of the first time derivative of the current frequency in the (i-l) -th period. Pulses with frequencies AU F (t -) and F | (t.) From the outputs of controlled frequency dividers 36 and 38 are fed to the inputs of frequency subtraction unit 28, the output of which forms a sequence of pulses with a mean frequency L. Р (t) - jf (t), proportional to the increment of the average value of the first derivative of the current frequency during the i-th period. In the controlled frequency divider 39, the frequency. &Amp; F {- (t) is divided by the factor Nj-. At its output, a sequence of pulses is formed with a frequency Fj (t) jn f (t) proportional to the average curtain value of the time derivative in the ith period of the current frequency. Pulses with a frequency F (t4) from the output of the controlled frequency divider 36 are fed to the input of the frequency multiplier 22. In frequency multiplier 22, frequency F. () is integrated over a time interval of the current (i + l) -ro period. At the output of the frequency multiplier 22, a sequence of pulses is formed with the average frequency dUu (b) kf4- (tf) t proportional to the current increment of the current frequency, depending on its rate of change, i.e. from the first derivative of the current frequency. V- Pulses with frequency F (t,) with you | HOD of controlled frequency divider 39 arrive at the input of frequency multiplier 20 and at its output a sequence of pulses is formed with average frequency F2 f fr r -tOt. This frequency is fed to the frequency input 21 and a pulse train is formed at its output with a mean frequency l Fr (t) -jf (t) t. The frequency AF-r (t, -) from the output of the frequency subtracting node 26 is fed to the input of the divider 29, the output of which is the PС, the frequency P - is fed to the input of the adder 25 frequencies, to the other inputs of which the frequency l kF-j- (t) is output of multiplier 22 frequency, frequency AF:}. (t) - from the output of multiplier 21 frequencies, frequency FT- (tf) - from the output of controlled frequency divider 34 frequency and signal sign 5-i% n U.Pr (t) - from the output of the node 26 subtraction frequencies. These frequencies, taking into account the sign of the increment sign of the current frequency l. F () is algebraically summed by the adder of 25 frequencies and at its output a sequence of pulses is generated multiplied by K of the current frequency at the {1 + 1) -th period F, (T ,,, t. IjViiHHt i t. The frequency at the output of the adder 25 frequencies corresponds to the current frequency multiplied by K times, corrected by the values of methodical and dynamic errors depending on the increments and derivatives of the first and second orders of the current frequency in the terminating period. Frequency pulses F (T |) from the output of the adder 25 frequencies start converter 1 code time slot at the output of which time pulses are formed, equal to the set frequency frequency reduced by a factor of K. These pulses are generated as follows: Each pulse of a given frequency passes through the prohibition circuit 17, embraces the memory register 15, then, pausing in the delay line 18, opens the gates 16, through which the code from the pulse counter 14 is rewritten from into the storage register 15, and having delayed in the delay line 19, zeroes the pulse counter 14, which begins to fill with pulses with a frequency Fg - from the output of the divider 23 frequencies. Since the zeroing of the pulse counter 14 is performed every period of a given frequency, then by the time of the survey, an NT-J code is generated at its outputs that is proportional to the period of the given frequency, which is stored until the end of the next period in the storage register 15. Each pulse of frequency F () s output of the adder 25 part sets the trigger 7 through the scheme OR 9 to the position closed by the output signal - fan 8, then h (holding the delay line 4, it (he delays counter 2, lingers in the delay line 5, he opens the valves 10, what Without which the code is rewritten from the memory register .15 into the subtractive counter 2, and finally, having lingered in the delay line 6, it enters the coincidence circuit 1 and the second input trigger 7, moving it to the position from the closing valve 8, through which pulses from the frequency fp from the output of the pulse generator 3 are received at the input of the subtracting counter 2. At the output of the subtracting counter 2, a zeroing pulse is generated at a time interval C f reduced K times the specified frequency period. The pulse from the output of the subtracting counter 2, being expanded in the pulse shaper 11, arrives at the second input of the coincidence circuit 12. If the period of the frequency F () is longer, then the impulse from the output of the counter has time to form. If the frequency period Ft (T.) Is less than Te / k, then the pulse at the output of the subtracting counter 4 2 does not have time to form, as the next frequency pulse F () arrives earlier, restarting converter 1. When the frequency period F () becomes equal to Г : D which corresponds to the frequency F, then to the coincidence circuit 11, the pulses arrive simultaneously and at its output a matching signal of the compared frequencies is generated. If the zero register memory register 15 and the code rewriting signal via valve 10 arrive simultaneously, the prohibition circuit 17 is activated and the signal to reset the recording register 15 is delayed until the code is overwritten from it. Due to the comparison of the period of a given frequency multiplied by K times with the period multiplied by K times the current frequency, corrected by the increment value for the expired period and the derivatives of the first and second order in time of the current frequency, which allows extrapolating the value of the current frequency in the current period Depending on the nature of this frequency change in the final period, the proposed device allows K to increase the accuracy of determining the time of coincidence of the compared frequencies and to expand the scope of application its for functions of changing the current frequency in time according to a non-linear law, having first and second derivatives, and covering most of the functions of changing signals in industrial control and measurement systems. Claims 1. Digital null-organ auth.St. No. 335685, characterized in that, in order to improve accuracy over a wide frequency range, frequency multipliers, frequency dividers, counters, a frequency adder, a frequency subtractor, rewriting nodes, controlled frequency dividers are inserted, the output of the pulse generator is connected to the first the inputs of the first, second and third controlled frequency dividers, with the first inputs of the first, second and third frequency multipliers and the input of the first frequency divider, the output of which is connected to the information input of the counter, the outputs of which enes first rewriting unit inputs, the outputs of which are connected to second inputs of the first, fourth and fifth frequency dividers actuated, the first output of the first controllable frequency divider is connected to the second node overwriting inputs, the outputs of which are connected to the second input

The third controlled frequency divider, the first output of which is connected to the inputs of the third rewriting node, the outputs of which are connected to the second inputs of the second controlled frequency divider, the first output of which is connected to the first input of the first frequency subtraction node, the output of which is connected to the first input of the sixth controlled divider frequency, the output of which is connected to the first input of the second subtraction frequency node, the output of which is connected to the first input of the fifth controlled frequency divider, the output of which is connected to the second input the first frequency multiplier, the output of which is connected to the second input of the second frequency multiplier, the output of which is connected to the first input of the frequency adder, the output of which is connected to the first input of the main device, the output of the second rewriting node is connected to the second input of the sixth controlled frequency divider, the second output of the first control frequency divider is connected to the second input of the frequency adder and the first input of the third frequency subtractor, the first output of which is connected to the third input of the frequency adder, and the second output - to the first input of the fourth controlled frequency divider and through the second frequency divider to the fourth input of the frequency adder, the second output of the third controlled frequency divider is connected to the second inputs of the first and third subtraction nodes

frequency, the first output of the fourth controlled frequency divider is connected to the second input of the second frequency subtractor and to the second input of the third frequency multiplier, output

which is connected to the fifth input of the frequency adder, the output of the first frequency divider is connected to the second input of the device.

2. Zero-body POP.1, characterized in that in it each of the controlled frequency dividers consists of a counter, register and rewriting node, the first input of the node connected to the information input of the counter, the output of which is connected to

the control input of the rewriting node and to the second output of the node, the second input of the node is connected to the input of the register, the output of which is connected to the first output of the node and to the input of the rewriting node,

the outputs of which are connected to the inputs of the counter.

Sources of information taken into account in the examination

1. USSR author's certificate 335685, cl. G About F 7/04, 11/24/69.