SU790217A1 - Pulse delay device - Google Patents

Description

one

The invention relates to radio engineering, in particular, to devices with a wide range of electronic adjustment of the delay time, and can be used in radar when measuring the coordinates of objects.

A device for delaying pulses is known, comprising a clock pulse generator, a coincidence element, operating and control counters, a control key, a trigger 1.

A disadvantage of the known device is the low accuracy of the time delay, since the output pulse is generated by the comparison circuit, which makes the delay accuracy dependent on the instability of the transfer propagation time in the working counter. Low delay accuracy is also due to the lack of synchronization between the delayed pulse and the clock generator. The presence of feedback on the zero bus of the installation of the working counter leads to the ambiguous formation of the duration of the output and pulse and the possibility of the occurrence of failures in the working counter.

It is known a device for lagging pulses, comprising a clock pulse generator, the output of which through a match element is connected to the working counter input, a control unit, a counter, a control key whose output is connected to the control counter input, a trigger, the output of which is connected to one of the element inputs coincidence, multi-input element of coincidence and P. two-input

10 elements of coincidence, and the one-bit outputs of the control counter through the two-input elements of the socket are connected to the one-bit inputs of the working counter, the outputs of which

15 is connected to the inputs of a multi-input matching element, the first input of which is connected to the output of a matching element.

A disadvantage of this device is the low accuracy of the time delay, which is carried out with an accuracy of up to + T, where T is the period of the clock pulse generator. This is due to the fact that

25 pulse not synchronized with the clock pulses of the generator. Another disadvantage of devices is the dependence of the delay time on the duration of the delayed pulse,

30 since the duration of the delayed

pulse, enters a delay time equal to

.

where K-S.O, 1,2 ...; T is the period of the generator of clock pulses; B duration of delayed pulse

The purpose of the invention is to improve the accuracy of the delay and the formation of a delay independent of the duration of the input pulse.

This goal is achieved by the fact that a device containing a clock pulse generator, the output of which is connected to the working counter input, a control counter, a control key, the output of which is connected to the control counter input, a trigger whose single output is connected to one of the inputs of the coincidence element, a multi-input coincidence element, rt of two tail elements of coincidence, and the one-by-one outputs of the control counter are connected to bit-by-digit two-input elements of the coincident counter The work counter moves, the outputs of which are connected to the inputs of the multi-input coincidence element, the first input of the latter is connected to the output of the matching element, three shaping elements are introduced, an additional matching element, a trigger trigger trigger generator and an inverter, and the inverter output is connected to the input of the first forming element, the output of which is connected to the setup input of the trigger for triggering the start-up of the clock pulse generator, whose single output is connected to the trigger input of the generator clock pulses, the output of the second formating element is connected to the fault inputs of both triggers, the input of the second formating element is connected to the output of the α-input input coincidence element, the output of the clock generator is connected to the input of an additional coincidence element, the second input of which is connected to the inverse output of the trigger output of the additional element the match is connected to the inputs of the two-input matching elements and to the input of the third forming element the output of the latter is connected to the mouth ovochnomu entry trigger, and inputs controlled switch connected to the terminal and the error signal input of the second forming member.

FIG. 1 shows a functional diagram of the device; in fig. 2 timing diagrams explaining the operation of the device.

The device contains a waiting generator of 1 clock pulses, elements 2 and 3 of a match, working counter 4, control counter 5, key 6,

controlled by the error signal supplied to terminal 7, triggers 8 and 9, multi-input element 10 coincidence, n, two-input elements 11 coincidence, forming elements 12, 13, 14, inverter 15.

The pulse delay device is operating; in the following way.

Before the operation of the device for pulse delay, a certain number K-1 is recorded into the control counter 5 using any of the known methods, which determines the required predetermined set value of the delay tjoA. . In this case, on the output inverse bits of the control counter, the number M 2 - K + 1 is set, where 1 is the number of bits of the control counter. Writing a number to the control counter is one less than the delay requires, due to the fact that the first pulse of the clock generator does not enter the work counter, but is used to rewrite the contents of the control counter into the work counter. When an input pulse arrives at the front edge 16 (Fig. 2a), it is inverted by the inverter 15 and a logical difference is generated in O (Fig. 25), i.e. on the leading edge of the input pulse. From this logical differential element 14 generates a pulse (Fig.), Which sets the trigger 8 in one state and a single output of the trigger 8 starts the waiting generator 1 clock pulses (Fig. 2d). The first clock pulse enters through the coincidence element 3 to the inputs of the two-input elements 11 and overwrites the contents of the control counter 5 into the operational counter 4 (Fig. 2D,

, "), And on the back

e, n

. l

45 front of this clock pulse (lo)

differential drop in

Claims (2)

element .12 forms a pulse, which sets trigger 9 to one state. The signal from the single input permits the passage of clock pulses through element 2 to match the input of the working counter, and the inverse output of trigger 9 blocks the passage of tact pulses through element 3 to match. Since the working counter has a total conversion factor, where N is the number of counter bits , for its overflow, the number k of pulses is necessary. When a working counter K-1 pulse arrives at the counting input, it is completely filled, and at all of its forward output bits, single states are set, which arrive at the coincidence element 10. At the moment when the K-th pulse arrives at the counting input of the working counter 4 and at the coincidence element 10. at the output of the latter an output pulse (Fig. 2n) is formed, equal to the duration of the pulse of the generator 1, which is fed to the output terminal 17 of the delay device. After the K-th pulse terminates at the input of the working counter, the latter overflows and it returns to the initial state. At the same time, the output pulse from the output of the coincidence element 10 is fed to the input of the key 6. From the output of the key 6, the pulse is fed to the counting input of the control counter 5 to add (or subtract) if there is an enable potential key on the control terminal 7, where the number changes to K or K-2. At the same time, on the falling edge of the output pulse from the output of coincidence element 10 (logical difference from to O), element 13 generates a pulse that resets triggers 8 and 9. Trigger 8 removes the start signal of generator 1. Trigger 9 blocks the single output of clock pulses in the work counter, and the inverse output gives permission for the match element 3. If necessary, make a delay relative to the trailing edge of the input pulse, it is required to be fed without inversion, and element 14 will generate a pulse along the trailing edge of the input pulse. In the future, the principle of operation is similar to the operation of the device when it is launched relative to the leading edge of the pulse. Thus, in this device for the delay of pulses, the high accuracy of the resulting delay is realized and the time delay does not depend on the duration of the delayed pulse. The invention of the device for delaying a pulse containing a generator of clock pulses, the output of which through a coincidence element is connected to the input of the operating counter, a control counter, a control key, the output of which is connected to the input of the control counter, a trigger, a single output j of the second match, multi-input, match element and two-input match elements, and the one-bit outputs of the control counter are connected to the bits through the two-input match elements The inputs of the working counter, the outputs of which are connected to the inputs of the multi-input coincidence element, the first input of which is connected to the output of the coincidence element, characterized in that, in order to increase the delay accuracy and delay formation independent of the input pulse duration, three shaping elements are added, the coincident element, the trigger trigger trigger generator, the inverter, moreover, the inverter output is connected to the input of the first forming element, the output of which is connected to To the input of the trigger trigger trigger input, the unit output of which is connected to the trigger input of the clock generator, the output of the second forming element is connected to the fault inputs of both triggers, the input of the second forming element is connected to the output of the multi-input element of the same day generator, match, the second input of which is connected to the inverse. the trigger output, the output of the additional matching element is connected to the inputs of the two-input matching elements and to the input of the third forming element, the output of the latter is connected to the installation input of the trigger, and the inputs of the control key are connected to the error signal terminal and the input of the second forming element. Sources of information, taken into account during the examination 1. USSR author's certificate No. 295194, cl. H 03 K 5/153, 26J09 9. 2. Authors certificate of the USSR 598224, cl. H 03 K 5/13, 09/27/76 (prototype).