SU786024A1 - Device for asynchronous interfacing of synchronous binary signals - Google Patents

Description

one

The invention relates to telecommunications and can be used for the input / output of synchronous binary signals to digital paths of systems with delta modulation and pulse-to-5 modulation.

A device for asynchronous coupling of synchronous binary signals is known, containing on the transmitting side a controlled distributor, the bit outputs of which are connected to the first inputs of the memory block, the second input of which is connected to the block, frame synchronization connected switchboard, frame alignment unit, controlled distributor and memory unit, the bit inputs of which are connected to the corresponding switch outputs, as well as an automatic frequency control unit (AC ), Whose output is connected to another input of the controllable distributor l.

However, the known device does not provide 25 high reliability of transmission with a possible defeat in the service information channel.

The purpose of the invention is to improve the accuracy of the match .30

For this purpose, an asynchronous interface of synchronous binary signals is contained in the transmitting side with a controllable distributor, the bit outputs of which are connected to the first inputs of the memory unit, the second input of which is connected to the frame synchronization unit, and at the receiving side - serially connected switchboard, unit cyclic synchronization, controlled valve and memory block, the bit inputs of which are connected to the corresponding outputs of the switch, as well as the AFC block whose output is connected to another input control unit distributor, serially connected start block, counter, comparison block, encoder and prediction block, whose output is connected to another input of the comparison block, and an additional input connected to the output of the trigger block and the inputs of the frame synchronization block and controlled distributor , the auxiliary output of which is connected to another input of the counter, and another input of the controlled distributor is connected to another output of the triggering unit, and the output of the encoder is connected to the third input b flash memory, and the reception side decoder administered serially connected and the prediction block, whose output is connected to the input of the AFC unit, and the other outputs frame synchronization unit connected to the inputs of the switch and the decoder, the other input of which ss1edinen of the additional output switch.

FIG. 1 shows the structural electrical circuit of the proposed device, the transmitting side; in fig. 2 the same, the receiving side.

The asynchronous interface of synchronous binary signals contains a trigger unit 1, a controlled distributor 2, a counter 3, a memory block 4, a frame synchronization block 5, a prediction block b, a comparison block 7, an encoder 3, a switch 9, a frame synchronization block 10, a decoder 11, prediction block 12, ALF block 13, direct e 1 distributor 14, memory block 15.

The device works as follows.

The start of operation of the device is recorded on the transmission of the moment of coincidence of the reference and clock pulses in the trigger unit 1. In particular, this can be achieved by using an adjustable signal-frequency delay line fc.

It is also possible to organize the start of operation of the device by forming on the transmitting side and transmitting at the receiving end a special code combination of the initial error in the phase of the reference and clock pulses.

The signal from the output of start-up unit 1 enables the operation of the controlled distributor 2, counter 3, block 5 of cyclic syncronization, and block 6 of prediction.

Controllable valve 2, clocked by frequency r, is a shift register with n + 1 input. Its start is the reference pulses from start block 1. At its outputs, clock pulses, the number of which between two adjacent reference pulses is counted by counter 3, serve as pulses to write the synchronous binary signal to the 4 block. After comparing the actual and predicted number of unit intervals in the cycle performed by comparison unit 7, the difference signal is sent to the encoder 8 deviations from the prediction and recorded in binary code in memory block 4.

The frame alignment unit 5 provides to the memory unit 4 a phase combination code cycle. The reading of information and service signals from memory block 4 is carried out at the frequency {c.

A cycle organized in a channel contains N unit intervals, of which m is used for information packets, and (S-i) -unit intervals for service assignments.

In the case when the cycle of signals of the clock frequency f. if there are more or less unit information intervals relative to the predicted number, then information about the number and nature of unnecessary or missing unit intervals is transmitted to service positions.

On the receiving side of the device (Fig. 2), the switch 9 sends signals from the channel along N corresponding circuits, of which they are reserved for informational pulses, and (N-h) - for service. Switch 9 is controlled by a frame synchronization unit 10.

The service signals from the switch 9 are decoded by the decoder 11, to the control input of which the reference pulses from block 10 are supplied.

If there is no deviation in the number of single information intervals in the prediction cycle, then prediction unit 12 changes the clock frequency -fg. in accordance with a predetermined periodicity of the number of unit information intervals in the cycle h, h + f. If this deviation exists, the prediction unit 12 corrects this number so that the corresponding cycle contains as many unit frequency intervals as how many were actually transmitted in the synchronous binary signal. The correction of the clock frequency c (according to a predetermined number of unit intervals in the cycle on the transmission) is carried out by block 13 of the AFC. The operation of this block is organized in such a way that the clock frequency fc varies from cycle to cycle in accordance with the prediction of the number of informational units. Hfcjx intervals in this and after cycles. As a consequence, additional correction of the frequency c will be required only in cases where P is different from the predicted one.

The controlled valve 14 is clocked by the recovered frequency 5, triggered by reference pulses from block 10.

The information outputs of the switch 9 are connected to the inputs of the memory block 15. . :

using the controllable distributor 14, the memory block 15 provides a recovered synchronous binary signal.

Claims (1)

In cases when the number of single information intervals fails in a certain cycle, then the periodicity of the sequence hjhilB remains unchanged, which is equivalent to shifting the sequence and, n-t-f, one step to the right or left on the number axis with respect to the predicted position. In order to phase in this case the predicted and actual sequences, a corrected forecast can be applied in the device. Its essence is that the transmission prediction unit 12 analyzes the phase correspondence of the periodicity of the predicted and actual sequence I, Vi t G and, if necessary, corrects the forecast. Information about this correction is transmitted to the receiving side of the device in free service positions, chi. The proposed conjugator of synchronous binary signals makes it possible to increase the reliability of transmission in comparison with the prototype. In the case of redundant overhead coding, in the proposed device, two unit service intervals are required for this, whereas in the prototype - three. Claims of an asynchronous interface of synchronous binary signals containing a controllable distributor on the transmission side, the bit outputs of which are connected to the first inputs of the memory block, the second input of which is connected to the frame synchronization unit, and serially connected switches a frame alignment unit, a controlled valve and a memory unit, the bit inputs of which are connected to the corresponding outputs of the switch, as well as the AFC unit whose output is connected to g The other input of the controlled distributor is distinguished by the fact that, in order to improve the accuracy of the interface, serially connected start-up unit, counter, comparison unit, encoder and prediction unit are entered on the transmitting side. The van, the output of which is connected to another input of the comparison unit, and the auxiliary input is connected to the output of the start-up unit and the inputs of the frame alignment unit and the controlled distributor, the auxiliary output of which is connected to another input of the counter, and another input of the controlled distributor and the encoder output is connected to the third input of the memory unit, and the serially connected decoder and prediction unit are input at the receiving side, the output of which is connected to the input of the AFC unit, and others The e outputs of the frame alignment unit are connected to the inputs of the switch and the decoder, the other input of which is connected to the additional output of the switch. . Sources, information taken into account during the examination 1. USSR author's certificate No. 510792, cl. H 04 J 3/00, 1974 (prototype). T f CAC