SU773646A1 - Function generator - Google Patents

Description

This invention relates to analog computing. A functional converter is known that contains P diode elements and implements piecewise linear approximation of functions. Its disadvantage is complexity and low accuracy. The closest in technical terms to the proposed invention is an functional converter containing the first and second adders, the multiplier, the first watches of the adders and the multiplier are connected to the input of the converter, the output of the first adder is connected to the second input of the multiplier, the output of which is connected to the second input the second adder, the output of the second sum of the torus is connected to the second input of the first adder, the third adder, the output of which is. the first and second inputs are connected, respectively, to the output of the second adder and to the reference voltage bus 2. A disadvantage of the known converter is the relative complexity and low accuracy due to the high sensitivity to the error of the multiplier. The purpose of the invention is to improve the accuracy and simplify the device. This goal is achieved by the fact that in the functional converter containing the first and second adders, the multiplier, the first inputs of the adders of the multiplier are connected and are the input of the converter, the output of the first adder is connected to the second input of the multiplier, the output of which is connected to the second input of the second adder, the output of the second adder is connected to the BrojM M input of the first adder, a third of the inputs of the first and second adders are connected to the reference voltage, and the output of the second adder is the output of the converter. The drawing shows the functional transducer circuit.

The device contains the first adder 1,. The multiplier 2, the second adder 3

The Converter operates as follows.

The inputs of the adder 1 receives the argument X, the reference (single) signal Z and the output signal V of the converter. The output signal of adder 1, having the form AX + Bl + V., 2., Is fed to multiplier 2, which multiplies by X. The output signal of the multiplier is summed with the argument and reference signal on adder 3:

(d, 2) x b2x + cr.

At B + B j BjZvl, the output signal of the converter is V

By optimizing the choice of parameters B and Bj, the sensitivity of the converter to the error of multiplier 2 is significantly reduced, and thus the conversion accuracy is increased.

The functional characteristic of the multiplier is

ZiX- -K.

H.CH

Where

- arguments;

2

-output signal;

TO

-coefficient taking into account the error of the multiplier.

The functional characteristic of the converter, taking into account the error of multiplier 2, has vice

V (AU.UV, ZS1U1-ЬЬ X + С: -il 3C-K

The coefficient of influence of the error of the multiplier 2 for the converter represented in the drawing is

av K (.Ch, t) s) x: (i-DxtF h

Coe (the influence of the error of the multiplier 2 for the known is

) HCh

di | 1-and-X «.1Ь.Ч

Naphshkyur, a1troks maci functions with preavpami change of the argument and methodological error O, 3% has the form

, “„ A.fe 2LX -bB75X-0; tSl, 457

When implementing this function, by the structure of the known, the influence factor of the error of the multiplier 2 is

oL -i, 15 touch

When implementing the function of the proposed scheme

we have

0 (60, PrMW, 0.5a,.

Thus, the coefficient of influence of the error of the multiplier 2 in the proposed converter is 5 times less in comparison with the known converter. It should be noted that the need for a reference signal in the proposed converter does not, as a rule, lead to additional hardware costs. At present, precision multipliers are based mainly on the compensation structure and require a reference signal, which can be used as a Z signal. Excluding the third adder leads to a reduction in hardware costs in the proposed converter by about 2% compared to the known .

Claims (2)

1.Smolov V. B. Analog computers. M., Higher School, 1972, p. 262. 2. Reference non-linear circuits. Subtitle D. Sheingold. M. / Mir, 1977, WITH; 56, FIG. 2, 1, 12a (prototype).