SU771682A1 - Device for converting vector polar coordinates into rectangular ones - Google Patents

Description

(54) DEVICE FOR CONVERSION OF POLAR VECTOR COORDINATES TO RECTANGULAR

one

The invention relates to the field of computer technology and can be used as part of calculators in solving problems associated with coordinate transformation.

A device for converting polar coordinates into rectangular, containing a strobe shaping unit, AND elements, a multiplication unit, a memory block, is connected by potential inputs to high-order buses of an input code, a switch and a quadrant switch.

Ij.

To the disadvantage of such a device

its complexity and insufficiently wide range of variation of the input frequency should be attributed.

The closest in technical essence is a device for converting polar coordinates into rectangular coordinates, which contains a switch, the first and second outputs of which are connected to the inputs of frequency dividers, the potential inputs of which are connected to the quad-switch switch outputs, the quadrant switch input is connected to the switch input, a potential input connected to the control output of the gate formation circuit, and a pulse input to the output of the circuit OR

The drawbacks of the device are the difficulty of servicing the ordinate function of the sines function, in the frequency-pulse form, which requires certain hardware costs, as well as a narrow range of variation.

10 input frequency, which is caused by the formation of sine and coscs values for two consecutive clocks.

The aim of the invention is to expand the range of input signals.

15

The goal is achieved by the fact that the device for converting the polar coordinates of the vector into rectangular, containing a memory block and a switch, the first VHO.COM which are connected to

20 to the output of the trigger interval, the first input of which is connected to the pulse input of the device, the first and second frequency dividers, the pulse inputs of which are connected to the corresponding

25 outputs of the simulator, and control inputs - respectively with the first and second outputs of the quadrant switch connected by the input to the quadrant code bus, the third output

30 quadrant jumper coupled

contains the second input of the switch; it contains the number-pulse multiplication unit, the comparison unit, the counter element And, the trigger trigger, the output of which is connected to the first input of the element And, the second input of which is connected to the reference frequency bus, and the output to the pulse input of the number-pulse multiplication unit , the potential input of which is connected to the output of the memory unit, the potential output - with the lower bits of the first group of inputs of the comparison unit, the first and second pulse outputs - respectively with the pulse input of the switch and with the input of the counter, the potential output of which is connected with the second input of the memory unit and with the higher bits of the first group of inputs of the comparison unit, and the pulse input with the first input of the trigger trigger, the second input of which is connected to the pulse input of the device, the second group of inputs of the comparison unit is connected to the task bus the argument of the vector, the output of the comparison block is connected to the second input of the interval trigger.

FIG. 1 shows a block diagram of the device; in fig. 2 illustrates embodiments of a number-pulse multiplication unit.

The device contains a trigger 1 trigger, an AND 2 element, a 3-pulse multiplication unit 3, a comparison block 4, a memory block 5, a counter 6, an interval trigger 7, a switch 8, a quadrant switch 9, frequency dividers 10 11. The position 12 denotes a pulse input of the device , 13 — Bus for setting the argument, 14 — bus for quadrant code, 15 — bus for reference frequency.

The 3 ° number-pulse multiplication unit contains (in the first embodiment, Fig. 2a) an element OR 16, And 17 elements, a counter 18. In the second version (Fig 2b) it consists of an adder 19, a register 20, a counter 21.

The device works as follows.

The polar coordinates of the vector, given by the pulse frequency Fy and the argument code N, are converted to rectangular coordinates in accordance with the expressions

(,) 4c

F. F sin

()

F - F cos

where 2 s, 2 2C, is the code number of the quadrant.

In the converter, with the arrival of a sc pulse, the input frequency Fy, the formation of a number-pulse codes

N (iK

s ,,.; п

, PE

KOTOpuo, depending on the quadrant number, are summed up on the corresponding dividers of frequencies 10 and 11, forming overflow pulses on their outputs.

 N. N.

ot vjSin

. -bile

a (t.,,

here m is the divisor of 10 and

0 11.

The peculiarity of the device is that the formation of the number of pulse codes and NCOS is ensured by deploying the sinus and cosine dependences over time. In this case, a piecewise linear approximation of functions by the expressions is used.

ot- cl

SinoC Z-CH AG S)

 Qt

2 -t-fz. -g

cosoi VUH) h-L)

where Zj, are the ordinates of the sine function at the i-cm approximation node.

5 Formation of number-pulse codes, and is carried out as follows.

To the installation inputs of trigger trigger intervals 7 and trigger trigger 1

Q receives frequency pulses F and translate them into single states. Trigger 1 permits the passage of the reference frequency FO to the input of block 3 (namely, to the input of counter 18 or 21)

- defined the beginning of the linear expansion of the argument code Nai (t) in it. In this case, counter 6 records the current code of the number of the partitioning interval along the axis of the NOH argument, which controls the selection from the memory block 5 of the increment codes of ordinates T during the interval.

,

where 2 is the approximation step.

As a result of the deployment of No ((t)

5 x moment of comparison, the number-pulse code is generated at the output of block 3

Ngin W 2 sinU.

Then, deployment begins at which trigger 7 changes its

0 state to the opposite and connects to the address inputs of the memory block 5 return codes (Nj) ots. During the further deployment of the argument (from NO / to 2) at the output of the block

3 a pulse number code is generated

cos

Thus, over the same period of the deployment of the argument, equal, the formation of the ", and N." takes place. Due to the smaller size of the cells required for storing increments, and due to the absence of a code-to-frequency converter in the memory 5, (about 15%).

Reducing the time for calculating H and Ncoft to one sweep of Noi (t) from O to 2 (in the prototype, N (t) from O to 2 is to be deployed twice), allowing the HTHb range of the input frequency to be doubled.

Claims (2)

Invention Formula A device for converting polar coordinates of a vector into right angles contains a memory block and a switch, the first inputs of which are connected to the output of the interval trigger, the first input of which is connected to the pulse input of the device, the first and second frequency dividers, the pulse inputs of which are connected to the corresponding output of the switch , and the control inputs, respectively, with the first and second outputs of the quadrant switch, connected to the input mode bus, the third output of the Quadrant switch is connected to the second the switch stroke, in order to expand the input signal range, the device contains a number-pulse multiplication unit, a comparator unit, a counter, an And element, and a trigger trigger whose output is connected to the first input of the And element, the second the input of which is connected to the reference frequency bus, and the output is connected to the pulse input of a number-pulse multiplication unit, the potential input of which is connected with the output of the memory block, the potential output with the lower bits of the first group of inputs of the comparison unit, the first and second pulse outputs - respectively with the pulse input of the switch and with the counter input, the potential output of which is connected to the second input of the memory unit and cTaixiDfMH bits of the first group of inputs of the comparison unit, and the pulse output - with the first input of the trigger S pa, the second input of which is connected to the pulse input of the device, the second group of inputs of the comparison block is connected to the bus specifying the vector argument, the output of the Compare block is connected to the second INPUT4 trigger of intervals. Sources of information taken into account in the examination of 1 USSR author's certificate 463986, class C.G G 7/22, 197. 2. USSR author's certificate 596955, cl. G About G 7/02, 1976 (prototype). T fl nkt .one