SU760100A1 - Microprogramme-control device - Google Patents

Description

The invention relates to the field of computing and can be used in radio systems, in particular to control the operation of a digital computer and a phased antenna array.

Yn firmware known device ⁵ systematic way in which to reduce the amount of equipment used branching microinstruction sequence (11.

A disadvantage of the known device is a large amount of memory block. ten

Of the known microprogram control devices, the closest in technical essence of the present invention is a microprogram control device, which contains a pulse generator connected to the input of the start-up node connected to the micro-command address counter input, the outputs of which are connected to the first group of inputs via the micro-command address decoder a microinstructions memory block, the second group of inputs of which is connected via an operation decoder ^ re-: command hub and command memory block with counter outputs to mand, connected to the entrance

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^; firmware control device. The outputs of the microinstructions memory block are connected through the register of microinstructions to the micro outputs! software control device, through re, position position transfer addresses hubs, AND elements and terminals with a transition counter input and transition addresses to c-registers, the switch is connected to the microcommand address counter inputs, while the switch control inputs are connected via a transition decoder to the conversion counter outputs and the reset circuit of the microinstructor address counter is connected to the input (2).

In the known microprogram control device, a memory block of micro-commands of large volume and a complex system of redirections of micro-commands taking into account transitions are used, which is a disadvantage of the known device.

The purpose of the invention is to simplify the device.

This goal is achieved by the fact that the firmware control device containing a pulse generator connected to the first input of the start-up node, the first output of which is connected to the counting input of: an address counter

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(microinstructions, the second output - with the control input of the transition decoder, the 'Troupe' control outputs - with the first inputs of the transition address registers, the third output - with the control inputs of the operation decoder and the command register; the input of the command counter is the first input of the device, and the output group is connected to a group of inputs of a microinstructions memory block, a group of outputs of which is connected to a group of inputs of a command register, a group of outputs _{10 of} which is connected to a group of inputs * of an operation decoder, a group of outputs κοτορο-,

It is connected to the first group of inputs of the microinstructions memory block, the second group of inputs of which is connected to the first group of outputs of the decoder of the microcommands address, the second input of the start-up node is connected to the corresponding output of the first decoder group "microcommands address, the group of address outputs, microinstructions memory block is connected to the second inputs of the transition address registers, the address output - with the control input of the start-up node, the group of information outputs - with the inputs of the microinstruction register, the first group of outputs of which is is Busy first trup- ₅ sing O device; transitions address registers outputs are connected to inputs of the group switch, the group of control inputs of which is connected with the group of transitions decoder outputs, and output - with the register address input · microinstruction counter, whose reset input is the second input of the device, and an output coupled to an input of the address decoder of microinstructions, the microinstructions comprises additional registers and the _group? microinstruction inputs additional registers coupled to inputs of the first register group Microcom the Andes, and the first group of vykVDbO (Ypl "'*" Nyto) VDBR <registers * l / ykroKomanU''^§Lyetsya'''

'^ the second group of device outputs, the control inputs of all microinstruction registers are connected to the corresponding outputs of the second group of the microinstructor address decoder, and the second group of outputs of all microinstruction registers is connected to the input decoder group of the transition decoder and is connected to the input of the start-up node.

The drawing shows a block diagram of a micro software control device.

The microprogram control device contains a pulse generator 1 connected ⁵⁰ '^'"'VcoDbm' of the start - stop 2 / 'link to the input of the microinstruction address counter 3, you’ll' • 'through' the microinstruction address decoder 4 to the first group of Inputs the microinstructions memory block 5, the second group whose input is connected through the operation decoder 6, the instruction register 7 and the instruction memory block 8 to the outputs of the instruction counter 9, sub20

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connected to the input 10 of the firmware control device. Some outputs of the microinstructions memory block 5 'are connected in parallel to the inputs to the registers of the microinstructions 11, where к is the Maximum number of phases of the operations performed (usually k = 5-7). The outputs of the 12 registers of micro-commands 11 '- 11 ^k are the outputs of the device. Other outputs of the memory block, micro-commands 5 are connected to the control inputs of the start-up node .2 and are connected via K-registers to the transition addresses 13 and the switch 14 to the inputs of the micro-commands address counter 3; The second microinstruction outputs of registers 11 '- 11 are connected in parallel ^to the inputs of the decoder 15 transitions, the outputs of which are connected to the control inputs of switch circuit 14. The reset microinstruction address counter 3 is connected to the input 16.

Firmware control device operates as follows.

When the microcommand 3 address counter is set to the zero state using an external pulse from input 16, when the reset signal is output from the corresponding register register output 11 or when zero information is written to it from the transition address register 13, the microprogram control device is set AND the initial state. Thus excited zero output of decoder microinstruction address 4 provides disabling input registers microinstructions 11 * - 11 ^k and node start - stop 2 which in turn provides ^- disabling input from the second register output transitions decoder 15 microinstructions 11 ¹ - 11 ^k and connect inputs register addresses transitions 13 ^'13-x to the outputs of the microinstruction storage unit 5 and inputs operations of decoder 6 to the outputs of the instruction register 7, wherein one of the outputs of the decoder bpo- ~' radios 6 excites a corresponding memory block address bus m krokomand 5 with codes and the start addresses of all phases used 'in the selected operation, and a number of control signals which correspond respectively to the address registers 13' transitions ^to-13; are used to start the start-up node - stop 2 and to connect the outputs of one of the registers of the address of transitions 1313 ^to through the switch 14 to the register inputs of the microcommand address counter 3 (only for the duration of the First impulse of each burst of pulses necessary for the scanning of microcommands for a particular phase of operation ). Thus, the first impulse of each pack, appearing at the output of the start-up node - stop 2, is fed to the control input of the transition decoder 15, thus ensuring the connection of the outputs

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one of the registers of the address of transitions 13 through the switch 14 to the register inputs of the micro-instructions address counter 3. At the same time, the most significant bits of the micro-commands address counter 3 are written! The code of the phase of the operation being performed (in the process of sampling micro-commands for this phase, it does not change later), which provides using the decoder of the micro-commands 4 address to connect the inputs of only one micro-command register 11 of the corresponding selected phase of the operation to the second outputs of the memory block micro-commands 5. In the lower-order bits of the micro-commands address counter 3, the starting address of the micro-commands zone of the micro-commands memory block 5 is written for the connected phase 15 operation. Further, upon receipt of the second, third, etc. pulses to the counting inputs of the micro-address address counter, all micro-instructions for the phase being executed are sampled.

In the last micro-command of each executed phase, the second output of one of the micro-command registers 11 generates a Start signal supplied to the corresponding input of the start-up node 2 and an address code is generated that is fed to the inputs of the decoder of turns 15 and used to connect the outputs of the next by succession of the register of the address of the transitions 13 through the switch 14 to the register inputs of the counter of the microinstruction addresses 3, after which the operation cycle is repeated. Only in this case are the microcommands with control signals selected from micro-commands of the micro-commands of the micro-commands 5, and these micro-commands are transmitted to the outputs 12 micrograms of the program control device through another register of micro-commands 11, corresponding to the current phase of the operation.In the last micro-command of the last executed phase of the operation - 45 The signal is fed to the corresponding circuit of the start-up node - stop 2, which ensures the installation of the firmware control device to its initial state, after which the working cycle you are repeating. _<5

In this firmware control device, in contrast to the well-known, additional micro-command registers and a number of new connections are introduced, which allows reducing the equipment • volume by eliminating the multi-bit register of positional transition addresses, the AND group, the OR element, the conversion counter, and the block storage volume reduction memory microinstructions because of OPPORTUNITY! storing words in it with a length of K-less than 55 in a known device, and because of the exclusion of the need to store in it. information for multi-bit positional

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addresses of transitions, as well as due to the equality of the register of micro-commands known? ... (prototype) of the device to the equipment of the registers of the micro-commands of the proposed device.

Claims (1)

Claim A firmware control device containing a pulse generator connected to the first input of the start-up node, the first output of which is connected to the counting input of the micro-command address counter, the second output to the control input of the transition decoder, the group of control outputs with the first inputs of the transition address registers, the third output - with the control inputs of the operation decoder and the command register, the input of the command counter is the first input of the device, and the group of outputs is connected to the group of inputs of the microinstruction memory block, gr ppa you, whose moves are connected to the group of inputs of the command register, the output group of which is connected, to the input group of the operation decoder, the group whose outputs are connected to the first group of microinstructions memory inputs, the second group of inputs of which is connected to the first group of outputs the micro-command address decoder, the second input of the start-up node is connected to the corresponding output of the first micro-command address decoder group, the group of address outputs of the micro-command memory block is connected to the second inputs of the address registers n Transitions, address output - with the control input of the start-up node, the group of information outputs - with the inputs of the microinstructions register, the first group of outputs of which is the first group of outputs of the device; the outputs of the transition address registers are connected to the switch input group, the control input group of which is connected to the transition decoder output group, and the output to the register input of the microinstruction address counter, the reset input of which is the second input of the device, and the output connected to the microinstruction address decoder input that differs in that, for the purpose of simplification, it contains additional registers of microinstructions, and the group of inputs of additional registers of microinstructions is connected to the group of inputs of the first register of microcomans And the first group of outputs additional registers microinstructions is the second group unit outputs, control inputs of the microinstruction register connected to the respective outputs of the second group address decoder microinstruction and a second group of outputs of the microinstruction register connected to a group of inputs of the decoder pe7 '' * '''^' ^: ..... 7 7 transitions and is connected to the start input of the start-up node.