SU758511A1 - System of multiple reception and conversion of analogue signals into code - Google Patents

Description

The invention relates to analog discrete converters and is intended, in particular, to create high-performance multi-channel reception and conversion systems into analog signal codes.

A known system of multichannel reception and conversion into an analog signal code, comprising a KONMyator of input analog signals, is connected via an output to an analog-to-digital converter (ADC) input, the code outputs of which are connected to the information inputs of a memory block 11J.

The disadvantage of this system is low throughput, since the conversion for each channel in it is performed in full-measure because it is not possible to use the results of the conversion of the previous conversion cycle in the subsequent one.

The closest in technical solution to the Vl.chet system of multi-channel reception and conversion into code / analog signals, containing a switch connected by address inputs to the first outputs of the control unit, the second outputs of which are connected to the first inputs of the memory unit, analog-digital conversion 5 A parallel-serial type, in which the analog subtractor is connected by the first input to the output of the switch, the second input to the output of the digital-to-analog converter, the third

the input to the third output of the control unit and the output to the input of the readout converter connected by the first and second outputs is correspondingly 5 but to the first and second inputs of the control unit and the third output to the inputs of the converters code — a code whose outputs are connected to the first inputs of the first and the second block of 20 recordings, the outputs of the first of which are connected to the first inputs of the reversible counter, the first outputs of the second recording block are connected to the first inputs of the register, the outputs of the 5th memory block are connected to the second inputs of the first and the second recording blocks, the third inputs of the recording blocks are connected to the fourth output of the control unit, the fifth and sixth outputs of which are connected respectively to the fourth inputs of the first and second recording blocks, the reversible counter outputs are connected to the first inputs of the digital-analog converter and the second inputs of the memory block these, the third inputs of which are connected to the output of the higher bit and code output 4 and the register and the second inputs of the digital-analog converter, the second inputs of the register and the reversible counter are connected to edmym output control unit, the eighth output being connected to the third input of the reversible counter. In addition, the ninth output of the control unit is connected to the fourth input of the reversible counter, and the second and third outputs of the second recording unit are respectively connected to the single and zero inputs of the high register bit 2.

The disadvantage of this system is low throughput due to the need to frequently perform an analog correction clock between conversion cycles.

The purpose of the invention is to increase the system capacity.

The goal is achieved. The system of multi-channel reception and conversion to analog signal code, containing a switch connected by address inputs to the first outputs of the control unit, the second outputs of which are connected to the first inputs of the memory block. An analog-to-digital converter of parallel-serial type where the analog subtractor is connected with the first JBXO-house with the switch output, the second input with the output of the D / A converter, the third input with the third output of the control unit and the output m - with the input of a read converter connected by the first and second outputs, respectively, to the first and second inputs of the control unit and third outputs — to the converter inputs, code code, the outputs of which are connected to the first inputs of the first and second recording blocks, the first outputs of which are connected to the first reversible counter inputs. The first outputs of the second recording unit are connected to the first inputs of the register, the outputs of the memory unit are connected to the second inputs of the first and second recording units, the third inputs of the recording units are connected to the fourth output of the control unit, the fifth and sixth outputs of which are connected respectively to the fourth inputs of the first and second recording blocks, the outputs of the reversible counter are connected to the first inputs of the D / A converter and the second inputs of the memory block, the third inputs of which are connected to the high-order bit and to the code outputs of the reg Istra and with the inputs of the digital-to-analog conversion. l, the second inputs of the register and reversible counter are connected to the seventh output of the control unit, the eighth output of which is connected to the third input 5 of the reversible counter, further comprises a trigger, a single-bit recording unit, delay elements, AND elements and OR elements, and zero input trigger connected to the output of the first

Q delay element, the output of the second

the delay element is connected to the third input of the control unit, the fourth input of which is connected to the trigger output and the first inputs of the elements And the second input of the first element And is connected to the fourth input of the second recording unit, the outputs of the second and third elements And are connected respectively to the inputs of the first and second elements delays, the second inputs of the second and third elements And are connected respectively with the output of the first and second elements OR, the first of which is connected to the third input by the first input

5 counters, the inputs of the third and fourth delay elements are connected respectively to the level and the single outputs of a single-bit recording unit connected by the first input to the upper register bit, the second input to the memory output, the third input to the single trigger input and with the third input of the recording unit, the fourth input - with

- the output of the first element And the output

The third OR element is connected to the fourth input of the reversible counter; the first input of the third IJSh element is connected to the second input of the first OR element and to the ninth output

0 of the control unit, the outputs of the fourth and fifth OR elements are respectively connected to the single and zero inputs of the most significant bit of the register, the output of the third delay element is connected to the second input of the third OR element and to the first inputs of the second and fourth OR elements, the second input of the last which is connected to the second output of the second unit

Q record, the third output connected to the first input of the p element. is OR, the second input of which is connected to the output of the fourth-drawn delay element and the second input of the second element

OR.

The drawing shows a block diagram of a multi-channel system for receiving and converting analog signals into code. The system contains switch 1,

0 memory unit 2, control unit J, analog-to-digital converter 4 of parallel-to-serial type, analog subtractor 5, read converter 6, pre-ra;

5 (D / A converter) 8, reversible counter 9, first record block 10, register 1.1, high order register 12, second record block 13, trigger 14, first 15 and second 16 delay elements, first 17, second. 18 and third 19 elements, first 20 and second 21 OR elements, one-bit write block 22, third 23 and fourth 24 delay elements, third OR 25 element, fourth 26 and fifth 27 OR elements The system works as follows.

During the first conversion cycle, when in block 2 there are still no codes, the corresponding values of the analog signals fed to the inputs of switch 1. In this system, as in the prototype, block 2 is loaded, in which on each channel of switch 1 full (push-pull) conversions. As a result, initial codes / corresponding to all input analog signals are generated and stored.

In the first conversion cycle, the subtractor 5 has a transfer coefficient of such a magnitude, second, when the input signal is equal to the maximum allowable range of input signals, the maximum position code is set at the outputs of converter 6, which are outputs of its comparators. This code is converted by the converter 7 to a binary code with a maximum value. Therefore, an input signal having any other value within the allowable range of variation is converted into a corresponding binary code with a value lying in the interval from O to. The code formed in the first clock at the outputs of converter 7 is then recorded through block 10 into counter 9, the outputs of which control converter 8. The output signal of the latter is subtracted from the input signal to be converted in subtractor 5, which r-also amplifies this difference signal. Thereafter, block 3 generates another level of the signal controlling the value of the transfer coefficient of the subtractor 5, which is increased 2 times compared to the value that occurred in the first conversion cycle. As a result, the difference signal amplified by a factor of 2 is brought to the same range of variation of the input signals.

Since in the considered parallel-series ADC the sensitivity of the comparators of the converter 6 is usually () times as large as the quantum of the converter, by the time the second clock begins to run, the value of the output signal of the subtractor 5 is often

beyond the range of input signals, which leads to the operation of one of the boundary comparators of the converter 6 and the appearance of the corresponding signal at its first or second output. The state of the signals at these outputs is analyzed in block 3. If one of them is present, block 3 generates a pulse that travels to the third or fourth input of counter 9, increasing or decreasing its content by one. At the same time, the output of the DAC 8 begins to change to the appropriate value. After some time, the maximum

5, the possible transient time at the output of the DAC 8 is set to a new value of the analog signal at the input of the converter. B. This consists of performing an analog correction cycle between the first and second conversion cycles.

The analog correction cycle ends at the moment the signal changes at the first or second output;: oh transducer b initiating this correction.

Then, block 3 performs the second cycle of reading the code from the outputs of the converter 7 to the register 11 via

0, block 13. Next, the code from the outputs of counter 9 and register 11 is rewritten into the appropriate cell of block 2, which results in the complete conversion of the analog signal on this channel.

After performing push-pull conversions on all channels of switch 1 and writing their result codes into the cells of block 2, unit 3 proceeds to perform the next conversion cycle. Starting from the second cycle, only the second conversion cycle is performed in the system. Moreover, the execution of this cycle begins with the recording of the code of the previous result of conversion from the corresponding cell of block 2 to counter 9 through block 10 and to register 11 through block 13. At the same time, unlike the prototype, in the system under consideration, the high bit 12

0 register 11, the code is written inversely: with respect to the value of the bit received by the 1st section of the k-th output of block 2. The inverse write operation to the most significant bit of the register is performed with

5, using the derived elements 22, 23, 24, 26 and 27. With the value O in this bit, the signal from the output of element 23 also goes through element 25 to the fourth input of counter 9, reducing its content by one.

Claims (2)

0 As a result of these operations, the code set in the counter 9 and register 11 is smaller by the code values stored in the corresponding cell of the block 2. This results in a relative shift of the comparison levels at the inputs of the comparators of the converter b by an amount equal to half the scale and eliminates the need to perform analog correction after recording the result code of the previous conversion if the input signal changed during the previous cycle by i. quanta. So, the introduction of a single bit record, Delay elements and AND and OR elements into the trigger system leads to a significant increase in its throughput, since analog correction cycles are practically eliminated, starting from the second conversion cycle. A multi-channel reception and conversion system for analog signal code comprising a switch connected by address inputs to the first outputs of a control unit, the second outputs of which are connected to the first inputs of a memory unit, an analog-to-digital converter of parallel-sequential type in which the analog subtractor is connected the first input of the switch, the second input with the output of the digital-analog converter, the third input with the third output of the control unit and the output with the input of the converter the read gate connected by the first and second outputs respectively to the first and second inputs of the control unit and the third outputs — to the converter inputs code code, the outputs of which are connected to the first inputs of the first and second recording blocks, the outputs of the first of which are connected to the first reversing inputs the counter, the first outputs of the second recording block are connected to the first inputs of the register, the outputs of the memory block are connected to the second inputs of the first and second recording blocks, the third input of the recording blocks is connected to the fourth output of the block The control, the fifth and the second outputs of which are connected respectively to the fourth inputs of the first and second recording blocks, the outputs of the reversible counter are connected to the first inputs of the D / A converter and the second inputs of the memory block, the third inputs of which are connected to the higher-order Yes, and the code outputs of the register and with the second inputs of the digital-to-analog converter, the second inputs of the register and the reversing counter are connected to the seventh output of the control unit, the eighth output of which is connected to the third input of the reverse th counter, characterized in that, in order to increase throughput, a trigger, a one-bit write block, delay elements, AND elements and OR elements are entered into it, the zero input of the trigger is connected to the output of the first-delay element, the output of the second delay element connected to the third input of the control unit, the fourth input of which is connected to the trigger output and the first inputs of the And elements, the second input of the first And element is connected to the fourth input of the second recording unit, the outputs of the second and third And elements are connected to Respectively with the inputs of the first and second delay elements, the second inputs of the second and third elements And are connected respectively to the outputs: The first and second OR elements, the first of which is connected to the third input of the reversible counter by the first input, the inputs of the third and fourth delay elements are connected to zero and single outputs of a one-bit write block connected by a first input to an output of a higher register bit, a second input to an output of a memory unit, a third input to a single input trigger and to a third input of the first recording unit, fourth input - with the output of the first AND gate, the output of the third OR gate connected with even; with the reversing counter's vertical input, the first input of the third OR element is connected to the second input of the first OR element and to the ninth output of the control unit, the fourth and i fifth OR elements are connected to the high and zero inputs of the high register, respectively, the third delay element is connected with the second input of the third element OR, and with the first inputs of the second and fourth elements OR, the second input of the last of which is connected to the second output of the second recording unit, the third output connected to the ne The first input of the fifth OR element, the second input of which is connected to the output of the fourth delay element and the second input of the second OR element. Sources of information taken into account in the examination 1.Shushkov EI and Tsodikov M, B. Multichannel analog-digital converters, L., Energie, 1975, p., 118, fig. 5-6. 2, Interference in digital technology - 71. Abstracts of the All-Union Scientific and Technical Conference, Vilnius, 1971, p. 167, fig. 1.