SU758221A1 - Device for transmitting and receiving discrete information - Google Patents

Description

The invention relates to automation and computing and can be used for the exchange of discrete information over a two-wire communication line between N subscribers (for example, a computer), the transmission and reception disciplines of which are set in advance or established by part of the codes of the received information. u

There are known devices for receiving discrete-’θ information, containing, a clock pulse generator, receivers, a counter, code selectors, registers, and a control unit p.].

A disadvantage of the known devices 15 is a low S. the speed of information exchange.

The closest in technical essence to the proposed is a device for transmitting and receiving discrete information, containing at the receiver-transmitter a clock pulse generator, the output of which is connected to the first input of the clock counter and through the delay line to the first input of the first element I , the first inputs of the receiver-sensor are connected to the second inputs of the clock counter, the outputs of which are connected through the first CC2

The code lecturer and the serially connected element are NOT to the synchronization input of the receiver-transmitter, to the first trigger input and to the output of the first OR element, the trigger output is connected to the first input of the second And element and to the receiver-transmitter output, the second input of which is connected to the first input of the third element And to the second input of the second element AND, the output of the second element AND is connected to the input of the first element OR, the third input of the receiver-transmitter is connected to the first input of the OR-NOT element, to the second input of which the output n is connected The first element And the output of the first code selector is connected to the second input of the first element And and to the second output of the receiver-transmitter, the second code selector and the third element And [2].

A disadvantage of the known device is the low speed of receiving information.

The aim of the invention is to increase the transmission rate of th reception of discrete information.

This goal is achieved by /

that the exchange register, the first 'inputs and the first

758221 ‘..... 4

the outputs of which are connected respectively to the fourth inputs and the third outputs of the receiver of the “-transmitter, output ⁴ - is connected to the second input of the parallel-serial register; clock pulse, 'output $

The third element AND is connected via the second element OR to the third input of the parallel-sequential register and with the information output of the receiver, the second output of the parallel-sequential register of keys to the second input of the third element AND, the synchronization input of the receiver-transmitter is connected to the input clock generator and the output element is NOT. 1.5

The block diagram of the device shown in the drawing.

Each device receiver-transmitter contains a clock pulse generator 1, a parallel-serial register 2, a clock pulse counter 3, a first code selector 4, a NOT element 5, a first element AND 6, a delay line 7, a second code selector 25 8, element OR NOT 9, trigger 10, second element AND 11, first element OR 12, third element AND 13, second element OR 14, second input 15 of receiver-transmitter, first output 16 of receiver-transmitter, third input 17 of receiver -transmitter, fourth inputs and third outputs 18, 19, 20 of the receiver-transmitter, the first inputs 21 receiver-transmitter, the second output 22 ·

receiver-transmitter, receiver synchronization output 23. ’

The device works as follows. '

The initial state of all N receivers-transmitters should ensure that "will block transmissions to the line at input 15 (ί = 1, 2, ...). · One of the subscribers must take the exchange initiative. Suppose that this subscriber is subscriber 1. 45

The initial logical state in the wires of the communication line is zero.

Subscriber 1, taking the initiative to send, sends information to the parallel-serial register 2, sets to. counter 3 initial state (for example, the additional code of the number of cycles of exchange), sets input 17 trigger 10 in one state, sets the output resolution 15 (level ’5 Logical.unit). This' level of the logical unit, transmitted through the elements AND 11 and OR 12, will turn on all the generators of clock pulses and, having set the permission to the element "AND 13, 40

allow passage through the element OR 14, to the wire of the code value of the communication line of the logical state of the first transmitted discharge from the parallel-serial register 2.

Clock pulses from the outputs of the generators will begin receiving information from the wire of the code value of the communication line. Sequentially shifting it in parallel-serial registers 2 Information shift occurs until the first code 4 selector circuit develops a high level of logical unit. This level through the element NOT 5 will provide: turn off all the clock pulse generators, set all triggers to the zero state 10. High output level of the selector 4 Provides resolution on the second input of the element And b. The third input will receive the resolution of the element 6 6, which will receive the level of the logical unit From the second selector 8. Through the delay line 7 to the first input of the element

.And b! will receive the last clock pulse exchange, which will set the trigger 10 in one state. The subscriber, analyzing the logical state of the outputs 16, 22, and 23, determines the further discipline of the exchange.

If the outputs 22 and 23 are in the state of logical zero, then the stop of the exchange occurred on the counter 3.

In this case, the subscriber who stopped the exchange must continue this exchange, removing the level of the logical unit from the output of the code selector 4

If the output 22 is in the state of a logical unit, and the output 23 is in the state of logical zero, then the information of the parallel-sequential register 2 is transmitted to other subscribers (including returned to the exchange register 2). In this case, the reset of the synchronization wire occurred from the First subscriber, which analyzes the information of the parallel-serial register 2i, if the code of the receiver-transmitter (one of the parts of the information code) that transmits in the next exchange cycle is not own, then it transfers the transmission control to the subscriber code, removing the transfer resolution from pin 15 and setting the initial state of counter 3.

Thus, the next exchange cycle can be started only by that subscriber whose trigger 10 remains in a single state after this exchange cycle (exit 17). On the next exchange cycle, this subscriber acts as a transmitter, and the rest as receivers.

Thus, the positive effect of increasing the transmission rate is due to the fact that ’there is no need for transmission of clocking pulses over the communication line.

Claims (1)

Claim Device for transmitting and receiving 45 discrete information containing on five 758221 6 receivers-transmitters clock pulse generator, the output of which is connected to the first input of the clock counter and through the delay line to the first input of the first element I, the first inputs of the receiver-transmitter 5 are connected to the second inputs of the clock counter, the outputs of which are connected through the first selector code and a serially connected element is NOT to the synchronization input φθ of the receiver-transmitter, to the first trigger input and to the output of the first OR element, the trigger output is connected to the first input of the second element and with the first output of the receiver-transmitter, the second input of which is connected to the first input of the third element AND and to the second input of the second element AND, the output of the second element AND connected to the input of the first element OR, the third input of the receiver transmitter 20 keys to the first the input of the WEDGE element, to the second input of which the output of the first element I is connected, the output of the first code selector is connected to the second input of the first element I and 25 to the second output of the receiver-transmitter, the second code selector and the third element I, characterized in that, in order to increase the speed of transmission of discrete information, a parallel-serial register is entered into the receiver-transmitter, the first inputs and first outputs of which are connected respectively to the fourth inputs and the third outputs of the receiver-transmitter, to the second input in parallel -sequential register is connected to the output of the clock generator, the output of the third element AND through the second element OR is connected to the third input of the parallel-serial register and to the information output n Receiver-transmitter, the second ’swarm output of the Parallel-serial register is connected to the second input of the third And element, the synchronization input of the receiver-transmitter is connected to the input of the clock generator and to the output of the HE element.