SU756598A1 - Self-sustained inverter control device - Google Patents

Description

The invention relates to electrical engineering, in particular to the field of control of electric generators, electric motors and converters, in particular to the control of high-frequency inverters in the presence of random interference in various control circuits,

According to the main auth. No. 690604, a device for controlling an autonomous inverter is known, comprising a generator, two switches, a start-up bus, three drivers, three AND gates, η three-AND common elements, a NOT logical element, two OR gates, a thyristor state control unit, a trigger and off pulse shaping unit. In a known device, when a random disturbance leads to a failure (violation of the common-mode operation of a device containing two switches, a shutdown pulse shaping unit, a monitoring unit, and a log ical circuits), which sets the oscillator. It is disconnected from the control circuits for a time T _and> . sufficient to restore the original mode of the elements to be repeated.

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switching on and the next switching on is done automatically [1],

The disadvantage of this device is that in cases where random interferences (malfunctions) are grouped over a small time interval, frequent switching on and off of the inverter with a pause T ^ is possible, which limits the functionality of the device.

The purpose of the invention is to expand the functionality of the device by setting a limited time interval for automatic control of the operation of the inverter with a permissible number of failures.

This goal is achieved by the fact that the device for controlling an autonomous inverter is equipped with an up to 20 equal delay element, a counter, a trigger, an And element and an indication and alarm unit, the Start bus being connected to the first inputs of the controlled delay 25, the counter and the trigger, the generator output is connected with the second input of the controlled delay element, the output of which is connected to the second input of the counter, the output of which is connected to the second input

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trigger, a single output of which is connected to the control input of the generator, the input of the display and alarm unit and the second input of the element I, the first input of which is connected to the output of the thyristors status control unit, and the output to the third input of the counter.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagrams of work.

The device contains a generator 1, a driver 2 connected to a logic element ZI, a driver 4 connected to a logical element 5 NOT, a logical element 6I, a driver 7 connected to a logical element 8 OR, η three-input elements 9 AND, switches 10 and 11, power thyristor switching circuit 12, switching off impeller formation unit 13, logic element 14 OR, thyristor state control unit 15, trigger 16, logic element 17 AND, controlled delay element 18 connected to the input of counter 19, output connected to input of flip-flop 20, AND element 21 and the block 22 indicating and signaling.

The controllable delay element 18 provides a delay for the time T ^ _a ^ = 5-Krtgt ^, where N is the expected number of failures in the device during the time Τ _{№ ο1%} ; Ν 'value usually lies within 2-6; T _p - pause, which is formed by the device; T _p = 0.5-1.5 s ·, T ^ is the frequency of the generator (usually G ^ lies in the range 10 ^ - 10 ⁵ Hz); K -) is a coefficient chosen from the condition of ensuring the ratio.

The value of K up _a > is determined by the expression K ΐ ,.

The number of pulses in the counter 19, at which it overflows (the capacity of the counter); equals Ν. When the counter overflows, a pulse is formed at the output, which is fed to the zero input of the trigger 20. The counter has inputs for setting zero. The initial setting from the signal from the bus "Start" and the subsequent? the cyclic setting in the “Operation” mode from the output of the delay element 16 occurs after the interval Τ _Μα χ.

The first input of trigger 20 receives a signal from the Start bus, the second receives a pulse of overflow of counter 19 in the interval T ^ <T _taei . The first input of element 21 also receives an enable pulse from trigger 20, and the second receives pulses from control unit 15. The display and alarm unit 22 indicates, depending on the status of the trigger 20, “Norm” or “Stop”, and sends to the central console signals about the state of operation.

The device works as follows.

At the Start command (Fig. 2a), an impulse starts to form for the scrapping of the 1st switching power circuit and at the same time counter 19 is set to zero, trigger 20 is set to the position when there is a resolving potential from its unit forming arm (Fig 2? Ι) at one of the inputs of the element 21I, which turns on the generator 1. After that, the generator 1 forms a continuous grid of frequencies for control circuits with a frequency (Fig. 2 <Л). These pulses are fed to a controllable delay element 18, at the output of which ’pulses with a period are formed (Fig. 2-c).

Consider the option of the device when there are no failures in the interval T ^, i.e. from the output of block 15 for a time period T ^ there are no pulses, i.e. t _about = 0, where m ₀ - the number of failures,

equal to 0 in the time interval T ·.

In this case, through element 21, the pulses from the output of the block 15 are not the passage of time T, since t _about = 0. Therefore, on the time interval T _l - = there is a periodic confirmation of the zero state of the counter 19 from the controlled delay element 18. Thus, when t _o = O, the device operates according to its own algorithm.

Consider the second case of operation of the device, when on the interval T ^ <T _{max the} number of failures n ^ xI / where GHz is the number of failures not equal to zero in the time interval T ^ ί In this

In the case of element 21, the pulses from the output of block 15 during the time T will pass in an amount equal to and the specified quantity will be recorded in counter 19, since pc - <C ,, a Τ .; , then upon arrival

pulse with an interval, the counter 19 is reset from the value "t _n " to the value "O". Thus, with _tl , the device operates according to its algorithm — that is, * the inverter is automatically controlled.

Consider the third case of the device, when on the interval T ^ m ^ the number of failures is equal.

In this case, through element 21 I will pass from block 15 on the time interval Tu 5 Tupek pulses in the amount of t _a %, which will fill counter 19 and before the next zeroing pulse with a period of Tupa *, the counter will have time to overflow, overflow pulse will arrive at the zero input of the trigger 20, which will form, prohibiting the potential for operation of the generator 1, close the input of the element 21 and transfer the display element from the "Normal" mode to the "Stop" mode. Thus, with N on the time interval ^ ^ * the device is deducted

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is turned on from automatic mode on and off.

Further work is possible only by manually pressing the "Start" button, i.e. with operator intervention.

Let us consider specifically, in accordance with the time diagrams of FIG. 2, the third case of the device operation, when N = 3, and I Shd "4. In this case, when the Start pulse arrives, an enabling differential is generated from the trigger 20 (Fig. 2 d.2), and the pulses arrive at the input of element 21, which pass to the input of the counter 19 (Fig. 2e). The capacity of the counter is three, therefore the third impulse (Fig. 2e) fills it completely. The counter is overflowing, the overflow pulse arrives at the input of the counter 19 (Fig. 2-JE, flip-flop 20 is transferred and the inhibitory potential (Fig. 2/2) is fed to the control input of the generator 1, 20

which stops the formation of a grid of frequencies (Fig. 202) and closes the input of element 21 I, through which the fourth pulse already does not pass (Fig. 2d). Further operation and transfer of the device to the automatic mode requires pressing the "Start" button.

The advantage of this device in comparison with the known is the expansion of the functionality 30 of the control device by setting the time interval and the number of failures on it, which allows automatic control of the inverter operation, i.e. If there are 35 favorable conditions (random, "rare" interference), the operation is performed in automatic mode, under possible adverse conditions (predetermined by the operator) - the device goes into an automated mode and preserves the operational reliability of the device in the presence of adverse working conditions.

Claims (1)

Claim Device to control autonomous inverter auth.St. No. 690604, characterized in that, in order to expand the functional capabilities of the device by installing a limited time interval for the automatic control of the inverter with the number of failures allowed on it, it is equipped with a controlled delay element, counting, trigger, And element and display and alarm unit the bus “Start” is connected with the first inputs of the controlled delay element, the counter and the trigger, the generator output is connected to the second input of the controlled delay element whose output is connected to o the second counter input, the output of which is connected to the second trigger input, the single output of which is connected to the generator control input, the input of the display and signaling unit and the second input of the And element, the first input of which is connected to the output of the thyristor state control unit, and the third counter input.