SU754331A1 - Electric circuit testing device - Google Patents

Description

The invention relates to a measuring technique and can be used to control the insulation resistance, test the electrical insulation strength of electrical circuits, as well as to search for extra connections between disconnected circuits of cable products, printed circuit boards, etc.

A device is known comprising a control unit, a clock driver, a group poll counter, a decoder, a key block, a switch, a poll type switch and a single poll counter.

M ·

The disadvantage of this device is low speed in the localization of circuits with low insulation resistance.

The closest in technical essence to the present invention is a device for monitoring electrical circuits, comprising an indication unit, a switch, an input and control unit, an address separation unit, a control clock register,

²

generator, prohibition element, memory block and register of addresses and commands [2].

The disadvantage of this device also lies in the low speed at the localization of circuits with low insulation resistance.

The purpose of the invention is to increase the speed in the localization of circuits with low insulation resistance.

This goal is achieved by the fact that in a known device containing a display unit, a switch, the closing contacts of the respective relays of which are connected to the first and second tires of the measuring unit, and the switch coils of the switch relay are connected to the outputs of the switch control unit, one control input of which is connected to the first output of the block input and control containing the indicator, and the second and third control inputs of the control unit of the switch are connected respectively to the first and second outputs of the block of the division ad-1 · ow, the first input to torogo coupled with

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the second output of the input and control unit connected to the measurement unit and the control clock register, and the memory unit input is connected to the fourth output of the input and control unit, the fifth output of which is connected to the input of the address register and commands, the bit outputs of which are connected to the bit inputs of the switch control unit , the control result registers are entered for the first and second addresses, the unequal elements, and the senior unit search unit, the sixth output of the input and control unit being connected to the second input of the separation unit addresses, the third and fourth address inputs of which are connected to the bit outputs of the address and command register, the inputs of which are connected to the memory unit, and the output is connected to the measurement unit, the fifth inputs of the address separation unit are connected to the outputs of the control clock register, the input of which is connected to the control input of the re - \ Gistra second address and the corresponding control inputs of registers. the control result and the first address register, the corresponding inputs of which are connected to the output of the measuring unit, and the first outputs of the control result registers and the first address through the elements

inequalities are connected to the register of the second address, the output of which is connected to the indicator, which is connected to the second output of the first address register and to the second output of the monitoring result register, the first output of which is connected. dinene with the input of the senior unit search unit, the outputs of which are connected to the sixth inputs of the address separation block, which contains the elements AND · —OR and the inverter, the first and second inputs of the address separation block are connected through the first AND – OR element to the first output of the address division block and the input of the inverter, the output of which is connected to the second output of the address division block, the third and fourth inputs of the address division block are connected to the First bit inputs of the first and second AND-OR elements, respectively, and the fifth block input address separation is connected to the second bit input of the second AND-OR element, and the sixth input of the address separation block is connected to the second bit input of the third AND-OR element, the output of which is connected to one of the inputs of the first AND-OR element, the other

the input of which is connected to the second input of the address division block.

The drawing shows a block diagram of the device.

₅ The device contains a control unit 1, a memory unit 2, a register of 3 addresses and commands, a register of 4 control cycles, a switch 5 containing a relay 6 ^,

62 "" · · θ2η ^with closing

10 pins 7 ^, 7 ^,. ·. . 7 ^ _n ^, 7? _and fixed contacts 8. 8 _P>

a switch control unit, a measurement unit 10 with tires 11, 12, an indication unit 13, an address separation unit 14 consisting of elements 15, 16,

17 AND-OR and inverter 18, the control result register 19, the first address register 20, the second address register 21, the senior unit search unit 22 and elements 201,. . . 23 _{tons of} inequality. The device works as follows.

The control object 24 is connected to non- ₂₅ moving contacts "8 μ... 8 _{And a} relay of 6 £, 6% _... , 6 _{gp of the} switch

5. The commands from block 1 input and control device is set to its original state, with the relay 6 |, 6 ^,

. . . $ ζηΑ '& 2η. switch 5 is turned off. In block 2 of the memory is recorded information about the controlled points of the object 24 of the control in the form of addresses of controlled points and control modes. Then, from the input and control unit 1, a signal arrives in the 4 control clock register, which sets the code 00 at its output. . . 01, and the inputs to and 3 elements 16 of the AND-OR block 14 address division receives signals of logical "1" and logical "O *, respectively. From block 2 of memory in the register of 3 addresses and commands, the address of the 1st controlled point is called. If the address has a logical "1" in the low order, element 15 AND-OR also produces a logical signal "1", which comes to the input 3 of the element 16 AND-OR and from its output goes to the corresponding input of the switch control unit 9. At the same time, the corresponding the inputs of the switch control control unit 9 come signals corresponding to These are the addresses of the monitored point, from the outputs of the register of 3 addresses and commands. As a result, one of the odd relays 6p works and the corresponding of the closing contacts 7 ± _... 7 _2p . £ connects the control5

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The controlled point of the control object 24 with the selected address to the bus 12 of the block 10, measurements. Then in the register of 3 addresses and commands the address of the next monitored point is called, and if it ends with "1", then the next monitored point will also be connected to bus 12 of measurement unit 10, and if the address has "O" in the youngest digit, then the elements 15, 16 AND — OR of the block 14 times — 0 address divisions also have 'O' at the outputs, and the inverter 18 is '1', therefore the signal from the output of the switch control unit 9 includes the even address of the relay that matches the selected controlled point 15 ABOUT,, . . . 6 _2η , the closing contact of which 7 ^,. . . 7 _2p connects the input of the control object 24 corresponding to the address recorded in the register of 3 addresses and commands to the bus 20 11 of the measurement unit 10. Thus, in the register of 3 addresses and commands, the addresses of all controlled points that are subject to control for separation are called. As a result, monitored points with even 25 addresses are connected to bus 11, and odd points to bus 12 of measurement unit 10. After that, the command from block 1, input and control with the help of block 10 measurement verifies the relationship between 30 two subsets of controlled points (even and odd). If there is a connection, then the first (lower) digit (K-code) of the register 19 of the control result is recorded Ί 'if there is no connection - 35

"ABOUT."

According to the signal from the input unit 1 and the control unit 9, the switch control unit 9 turns off the relays 6 ^, 6 ₂ ,. . . 6 _2η _ | , 6 _2p switch Biv register 4 clock cycles control is made to shift the code to the right by one digit, after which the code at its output 00 ... 010 has a '1' only in the second digit. Again, the register is searched through the register of 3 addresses and commands of all addresses of controlled points that are to be checked for separation, and controlled points with addresses containing '1' in the 2nd digit are connected to the bus 12 of the measurement unit 10, and points with '0' in The 2nd digit is connected to the bus 11 of the measurement unit 10. A command from the input and control unit 1 is used to measure the connection between two new subsets using the measurement unit 10, and in the 2nd digit of the X code, a '1' is written when

31 6 detecting the connection and 'O' - in its absence.

All relays are switched off again br 6 ₂ "

• - · θΖη-1 '®2p switch 5, is moved one digit to the right' 1 "in the register of 4 control cycles and the third control cycle is performed. At the same time, controlled points whose addresses have" O "are connected to the bus 11 of the measurement unit 10 3rd digit and to the bus 12 measurement unit 10 - controlled points with addresses that have a '1' in;

3rd digit. When a connection is detected in the 3rd digit of the K - code, the '1' is written, in the absence - “O”. This principle is produced (n control cycles and the m-digit K “ ^K ° D is formed ⁱⁿ register 19 of the control result. If, after the t-th bar in register 10 of the control result, only zeros were found in all digits, then ego means that There are no superfluous connections, and the check ends there.

If at least one digit contains "Ι", which means that there is at least one extra connection, another diagnostic cycles will be performed (setting the address of the extra communication). In this case, unit 1 issues a command to turn off the relay br 62,. . . 6 _2η _ _{: 1} , 6 _2g) on the shift to the right by one digit of the register 4 control cycles, and at the input of the k-th element 16 AND-OR is set to "O", and at the input 3 - '1 *. In the first diagnostic cycle in the register of 3 addresses and commands, the addresses of P points are sequentially called, controlled for the absence of unnecessary connections. From the register 4 control cycles to the second inputs of the element 15 AND-OR code 00 is received. . 01, having a '1' only in the low-order. Therefore, at the output of the element 15, an AND-OR signal appears in the case when the address of the controlled point in the register of 3 addresses and commands is in the low-order -Ί '. The unit 22 for searching for the highest unit has the output t - a bit 'code with a single' 1 ', which corresponds to the highest ϊ -th digit of the control code (K-code) in register 19 of the control result containing Ί'. At the output of the element 17 AND-OR signal appears only when the address of the controlled point in the register of 3 addresses and commands has a '1' in | On the discharge, and at the output of the element 16 AND — OR the signal appears only at addresses in register 3

addresses and commands containing '1' in

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• eight

younger and] th discharges at the same time. According to these addresses, the odd ones of relay 6 are triggered | , θ2 "-ί * The closing contacts 7 ^ .... 7 _2ηΗ relays 6 | _,. . . controlled

points of the control object 24 with addresses containing "1" simultaneously in the ΐth and 1th digits are connected in the first diagnostic cycle to the bus 12 of the measurement unit 10, and all other controlled points to the bus 11 of the measurement unit 10. If measurement unit 10 gives a signal that there is a connection between the subsets of monitored points connected to buses 11, 12, the 1st digit of register 20 of the first diagnostic code address (c3 ₁ code) is written "1" if not that".

Next comes the 2nd diagnostic tact.

In register 4 control cycles from block 1 20

input and control signal is received shift to the right by 1 bit. All η addresses are searched again. Moreover, the controlled points, whose addresses have Ί "in the 2nd w / w] -th digits, 25 are connected to the bus 12 of the measurement unit 10, and all the rest are connected to the bus 11 of the measurement unit 10. A 2nd bit is formed - a code by analogy with 1 —Th, etc., to the tth digit. It should be noted that in the] —th digit, the code will always be “1”, since the subsets of points connected to the buses 11, 12 of the measurement block 10 in this cycle coincide with the subset of the] -th control- 35 clock cycle, and in the] -th digit of the K-code the "1" is always recorded. Therefore, the] -th diagnostic step should be programmatically excluded.

After the W-th diagnostic clock 40 in the register 20 of the first address is the address of one controlled point, incidental to the existing extra connection.

This address can be displayed on the display unit 13. Address 2 2nd kongrolirue- my point 45, is incident extra connection is obtained by logical processing -Codes K ISC via elements 23R ... 2Z nonequivalence _n, the inputs of which receives signals from the bitwise direct and inverse outputs of registers 19,

20 control results and the first address. Each digit of the ΰρ-code at the output of the elements 23 | , . . 23 _{tons of} inequality is formed in accordance with the formula 1 ι and is written in

^ register 21 of the second address 21. From the register 21 of the second address the address is the 2nd

controlled point displayed on the block 13 of the display.

During one test cycle, which includes w supervising and u-1 diag ⁵ sting cycles, one is detected

malfunction. If the object contains

malfunctions, then to diagnose them

It is necessary to perform проверки cycles of verification, and after the localization of the next fault, it must be eliminated.

Claims (3)

Formula from O'bregeNI 1. A device for monitoring electrical circuits containing a display unit, a switch, the closing contacts of the corresponding relays of which are connected to the first and second tires of the measuring unit, and the switch coils of the relay are connected to the outputs of the switch control unit, one control input of which is connected to the first output of the input block and control, containing the indicator, and the second and third control inputs of the control unit of the switch are connected respectively to the first and second outputs of the address separation unit, the first input of which is It is connected to the second output of the input and control unit, connected to the measurement unit AND to the register of control cycles, and the input of the memory unit is connected to the fourth output of the input and control unit, the fifth output of which is connected to. the input of the register of addresses and commands, the bit outputs of which are connected to the bit inputs of the control unit of the switch, characterized in that, in order to improve performance in localizing circuits with low isolation resistance, registers of the result of control of the first and second addresses, unequalities elements and search block are entered into it the senior unit, the sixth output of the input and control unit is connected to the second input of the address separation unit, the third and fourth address inputs of which are connected to the bit outputs p The register of addresses and commands, the inputs of which are connected to the memory unit, and the output is connected to the measurement unit, the fifth inputs of the address division block are connected to the outputs of the control clock register, the input of which is connected to the control input of the second address register and the corresponding control inputs of the control result registers9 754331 LL and the first address register, the corresponding inputs of which are connected to the output of the measurement unit, and the first outputs of the control result registers and the first address are connected to the second address register, the output of which is connected to the indicator, which is connected to the second output of the first address register and to the second the output of the register of the result of the control, the first output of which is connected to the input of the senior unit search block, the outputs of which are connected to the sixth inputs of the address division block. 2. Device by π. 1, about t l and tea! This is because the address division block contains AND-OR elements and an inverter, the first and second inputs of the address division block are connected through the first AND – OR element to the first output of the address-separation block and the inverter input, the output of which is connected to the second block output section 10 address, the third and fourth inputs of the address separation unit are connected to the first bit inputs of the first and second elements, respectively 5 AND-OR, and the fifth input of the address division block is connected to the second bit input of the second AND-OR element, and the sixth input of the address-separation block is connected to the second bit input of the third, 0 th AND-OR element, the output of which is connected to one of the first inputs element AND — OR, the other input of which is connected to the second input of the address division block. AT