SU742946A1 - Device for solving partial differential equations - Google Patents

Description

The invention relates to computing and can be used in the design and development of specialized devices for solving partial differential equations.

It is known a device based on the principle of bit-analog information processing, consisting of a bit-logic matrix built on valve circuits, on output buses of which sequences of pulses corresponding to the pair products of the digits of the numbers supplied to the reversible adder inputs are the output of which produces a solution to the finite-difference equation 1.

The disadvantages of the known device are the large amount of equipment associated, for example, with the need to use 2-input adders for n-bit numbers | the difficulty of automating the solution process associated with the generation of voltages controlling the discharge logic matrix; difficulties in developing mathematical software associated with the problems of obtaining discharge equations that are different from the original finite difference equations.

The closest to the invention in its technical nature is a device comprising an input unit connected to an adder, a multiplication unit, two serial-parallel registers connected by outputs to a multiplication unit, and step-switching units, whose inputs are connected to a multiplication unit connected to an adder, the output of which is connected

15 with the entrance of one of the registers. This device contains blocks that allow you to store two values of the grid function on the previous time layer and on this target, and also to multiply these values by the necessary coefficients in the blocks of multiplication, which makes it possible to solve the heat equation 2.

The disadvantage of the device is

25 that the accuracy of the solution implemented by the device does not exceed the second order of accuracy with a uniform grid and the first order with a non-uniform grid.

thirty

The purpose of the invention is to improve the accuracy of the device.

The goal is achieved by the fact that the device for solving partial differential equations containing registers, a multiplier, an adder, a switch, the output of the first register connected to the first input of the multiplication unit, the output of which is connected to the input of the adder, the output of the adder The second register, which is connected to the first inputs of the switch and the third register, the output of which is connected to the third input of the multiplication unit, the input register register and the second inputs of the third and third registers The third inputs of the second and third registers and the second input of the switch are connected to the control input of the device, the output of the switch is the information output of the device, the function for calculating the moments of the function is entered, the input of which is connected to the output of the second register, and the output of the calculator The functions are connected to the third input of the multiplication block, and also by the fact that the function’s moment calculation block contains two multiplication nodes, two adders, an input node, a division, and registers, and the first register is connected to the first input of the first node multiplied-and, the output of which is connected to the first input of the first adder, the output of which is connected to the first input of the division node, the first and second outputs of the input node are connected respectively to the first and second inputs of the second node multiplying, second and the third inputs of which are connected to the first and second outputs of the division node, the first and second outputs of the second multiplication node are connected to the first and second inputs of the second adder, the third input of which is connected to the third output of the division node, the third the output of the input unit is connected to the second inputs of the first multiplication unit and the division node, the third input of which is connected to the h-fourth output of the input node, the FIFTH output of the input node is connected to the second input of the first adder, the third, fourth and fifth inputs of which are connected respectively via the second, the third and fourth registers with one information inputs of the function moment calculator, the other information inputs of which are connected, respectively, to the input of the first register and to the second input of the input node, the output of the second adder is with information output of the function moment calculator

The drawing shows the block diagram of the device.

The device for solving differential equations in partial derivatives contains registers 1-3, multiplication unit 4, adder 5, switch 6, function moments calculating unit 7.

Block 7 includes registers 8-11, input node 12, multiplication nodes 13 and 14, division node 15, adders 16 and 17.

The algorithm implemented by the device is obtained by replacing the second derivative equations.

lf

moments of the function U, and the first derivative with respect to the finite-difference relations, which leads to the equation

. . , and

-JK., J QC

l

 Wk.,; -F,

x-, 3

which is calculated by an explicit iterative formula of the form

i, n-t, s. , m, 5, 5 J.,. ,, .. where the calculation of the moments of the functions occurs when solving the following systems of algebraic equations:

/ k ,. .4-d .d. .fc m11 :,

.B K.J KJ + I

;. ,,,. 4Д - .. ...:

.J t.l Ktl.,

THIS solves the equation

,,.

in as well

- S ,.S.A. - fti d

 c,

Where A, C.,

B - the value of the difference coefficients of the form

A, M, .., + C, -M ..

 d j i d - matrix of the right part

The operation of the device is as follows.

Registers 1-3 are entered by initial conditions and uP, j, I, | - These values are multiplied in lock 4 by the moments of the functions Kj and HELL, which arrive at the input of block 4 from the output of block 7. The resulting products are added to adder 5 and entered into register 2 as the 1st iteration of the decision on the 1st time layer. Similarly, it turns out 2-a, etc. iteration of the desired solution. With this block 7 computeD

lt moments of function ..

K, j mHiS-zj)

V.V

Claims (2)

and the switch 6 connects the output of the device to the inputs of neighboring devices to which the current value of the solution received in this device is connected to the control signal. At the end of the iteration process, the control signal from register 2 to register 3 records the solution obtained at the first time layer, and the initial condition and cJ- is entered into register 2. Similarly, the device operates on the 2nd, etc. in the nth temporal layer. The operation of block 7 at the 5th iteration n of the time layer occurs as follows. The registers 8-11 contain the initial conditions,,, U ,. respectively. At node 12, from the output of register 2, the current value of the solution arrives, and, at its other input, the prepared initial values,,, B, fb, arrive at node 12. At node 15, from the output of node 12, the values are received. 16 is the difference C. And, where formed by node 13. The values arriving at the input of node 15 are obtained by summing 16 values on the adder, and, stored in registers 9-11. The obtained values of the driving coefficient. i and value About j-. arrive at node 14, to which the values LL and b are simultaneously fed from node 12. The resulting products +) 1 are summed on adder 17 with the value B - :: .- T-7-T coming from the output Ad of node 15. The resulting sum is The current moment value of the function i4, (where.), continuously reflects the behavior of the AND function in the solution domain. The implementation of the proposed device can be carried out on the basis of K 178, K 186, K 502 series microcircuits. The introduction of an additional block for calculating the moments of the function distinguishes the proposed device from the known one, since it allows one to solve an important class of problems described by parabolic and elliptic equations accuracy and speed, increased by three orders in the case of a non-uniform grid and two orders in the case of a uniform grid, compared with the known. Claim 1. Device for solving differential equations in partial derivatives containing registers, multiplication unit, adder, switch, with the output of the first register connected to the first input of the multiplication unit whose output is connected to the input of the adder, the output of the adder whose output is connected to the first inputs of the switch and the third register, the output of which is connected to the second input of the multiplication unit, the input of the first register and the second inputs of the second and third registers The third inputs of the second and third registers and the second input of the switch are connected to the control input of the device, the output of the switch is the information output of the device, which is so that, in order to improve the accuracy, a calculation block is entered into it moments of the function, the input of which is connected to the output of the second register, and the output of the function’s moment calculation unit is connected to the third input of the multiplication unit. 2. The device according to A.1, which is based on the fact that the block for calculating the moments of the function contains two nodes more than 1 and. two adders, an input node, a division node and registers, the output of the first register connected to the first input of the first multiplication node, the output of which is connected to the first input of the first adder, the output of which is connected to the first input of the division node, the first and second outputs of the input node are connected respectively to the first and the second inputs of the second multiplication node, the second and third inputs of which are connected to the first and second outputs of the division node, the first and second outputs of the second multiplication node are connected to the first and second inputs of the second adder, the third the input of which is connected to the third output of the division node, the third output of the input node is connected to the second input of the first multiplication node and the division node, the third input of which is connected to the fourth output of the input node, the fifth output of the input node is connected to the second input of the first adder, third, fourth and the fifth inputs of which are connected respectively to one information input of the function moment calculator, other information inputs of which are connected respectively to the input of the first register and to the second input of the input node, the output of the second mmatora is a data output unit calculating moments function. Sources of information taken into account in the examination 1. G. Pukhov. Parallel-to-serial digital grids for integrating differential equations. Electronics and Modeling, vol. 3, Kiev, 1974. 2. Authors certificate of the USSR 373735, cl. G 06 G 7/56, 1971 (prototype).