SU739478A1 - Multichannel programmed control system - Google Patents

Description

730476

The OR OR delay block and the ontrol block, whose input is connected to the perm input of the output command block, bto) bie; ahrdy, which is connected to the first voltage register of the shift register; the second, the outputs of which are connected to the inputs of the second display unit, trigger, the first input - with the set of the cycle duration adjuster, u and the second input - with the output formed signals and with the second input of the second element OR, the second inputs of the first element And are connected to the codes of the amplifier unit, the second input of the unit is The supports are connected to the output of the control unit by the executive unit, the second input of the first element I is connected to the output of the control unit, and the third input to the first output is divided by the frequencies connected by the second output to the input of the start time selector, and the second outputs of the second counter are connected to the inputs of the fourth display unit

The drawing shows a functional 25 device diagram.

The device contains a master oscillator 1, a frequency divider 2, a start block 3, the first element 4 OR, the first counter 5, the first indication block 6, the time interval setting block 7 30, the amplifier block 8, the technological operating mode modes block 9, consisting of setting device 10, start-up time, second counter I, first element 35 And 12, fourth indication unit 13, forkshrevatel 14 signals, trigger 15, secondary element 16 OR, delay unit 17, control unit 18, second element 19 And, setpoint 20 long-40 ti cycle, register 21 shift , the second display unit 22, the output command unit 23, the third display unit 24, a reset button 25. In addition, the device has executive control units 26, power supply 27,. a reset unit 28.

The number of control blocks of the operating time modes is determined by the maximum number of products, while simultaneously passing the operating time, their operation is the same for all products. Therefore, the operation of the device is considered only the days of a single product.

The master oscillator 1 generates 55 pulses, which through a divider 2 frequencies and the first element 4 OR are fed to the first counter 5, the outputs of bits

Claims (2)

which are connected to the first display unit 6, and through the amplifier unit 8 to the first element 12 OR of the operating mode control unit 9. The initial real-time setting after turning on the device is performed by the start-up unit 3. Upon reaching 24 hours, the counter should return to its original state, this is accomplished by block 7 of the time interval setting. When the product is installed on the technological operating time by the start time adjuster 10, a code corresponding to the start time of the operating time is recorded into the second counter 11, which is recorded in the fourth display unit 13. When the counter codes 5 and 11 coincide, the first element 12 I triggers and, through the circuit, the signal shaper 14 sets the trigger 15 into one state, thereby allowing the passage of pulses from frequency divider 2, and the second element 19 AND to cycle duration 20. At the same time, the signal from the driver circuit 14 of the start signals is fed to the shift register 21, 21, having recorded the initial unit. Since the output of each register bit is connected to the output command block 23, this ensures the inclusion of the product undergoing operation and setting a predetermined operating mode. The outputs of the shift register bits are also connected to the second display unit 22, in which And | the first mode of operation. After the run-cycle run-out cycle 20 has expired, the clock pulse enters the shift register, advances the recorded unit to the second register bit, thereby setting the second operating time mode, etc. After the technological time has elapsed, the shift register, made on the basis of a ring counter, returns to the initial state and the initial operating mode is set. At the same time, the pulse from the output of the shift register sets the trigger 15 to the initial state, thereby prohibiting the supply of pulses to predate 20 cycle times. The register code signal C is also supplied to the end of time indication display unit 24. At the time of switching modes, in order to eliminate false operation of the unit 18, the control of the product, using the second element 16 OR and block 17 of the delay, the signal from the block 23 of the single commands to the input of the control unit of the product is stopped. If the product does not impose a technological bridle (control unit), the control unit 18 triggers and the signal from its output prohibits the supply of pulses from the frequency divider through the second i9 element And to the cycle duration setter 20, thereby switching the operation modes. the operating time indicates the mode in which the malfunction of the product has been made, which facilitates troubleshooting. The signal from the output of the control unit also goes to the unit 23 output commands and turns off the product to the outgoing operating time Thus, the use of this device simplifies the connection and maintenance of products, makes it possible to independently set up and remove products from operating time, relieves them from direct participation in the technological development of personnel, carries out continuous monitoring of the operation of the products. control, containing Consecutively connected master oscillator, frequency divider, the first element OR, one of the inputs of which. connected through the start-up unit to the second output of the frequency divider and the first counter connected to the nepJBorb input of the display unit, the second inputs and output - k output and input of the temporary interval assignment unit, and the third outputs - to the amplifier block inputs, and in each channel. control display units and an output command block, the outputs of which are connected to the inputs of the control unit of the executive unit, characterized in that, in order to expand the functionality of the device, a shift register and a series of start time setters, the second counter, the first element I, are entered into each control channel, signal conditioner, trigger, second AND element, cycle duration master, second OR element, delay unit and control unit, the output of which is connected to the first input of the output coma block ND whose second inputs are connected to the nefvvam code of the shift register, the second inputs of which are connected to the inputs of the second display unit, the third input to the input of the third display unit and the second trigger input, the first input with the output of the cycle duration setter, and the second input with the generator output signals and with the second input of the second element OR, the second inputs of the first element I are connected to the outputs of the amplifier unit; Element I is connected to the output of the control unit, and the third dispatch is; to the first output, the frequency divider connected by the second output to the start time master input, and the second inputs of the second counter are connected to the inputs of the fourth display unit. Sources of information taken into account during the examination 1. USSR author's certificate N9 532860, cl. q On R. 9/00, 1974. 2. Authors certificate of the USSR 411435, cl. Q 05 B 19/18, 1971 (prototype).