SU708303A1 - Programme-control device - Google Patents

Description

(54) SOFTWARE CONTROL DEVICE

one

The invention relates to the field of automation and can be used in various fields of industry in control systems of on-off objects as a function of time, for example, for programmatically controlling the transition process of switching regenerative heat exchangers of air separation plants.

A device for software control is known, which contains a timer loaded on the search relay, elements for switching off the latter and a feedback circuit 1. The device has the disadvantage of losing information during certain cycles at the time of switching the relay seeker, which does not allow to form complex control programs . to. it works in the “running unit” mode, to implement a code of the form 2 with a numerical value: 1-2-4-8-16, etc., which, as is known, does not possess redundancy.

The closest technical solution to this invention is a software control device comprising AND elements, the output of each of which is connected to the input of the corresponding memory element, a code generator, a source of trigger pulses, a clock generator, and timer 2.

The disadvantages of this device are cumbersome and CvTo HOCTb circuits and, as a consequence, the reliability of operation is potentially low.

The purpose of the invention is to increase the reliability of the device by the fact that a blocking node is inserted into the device, the triggering input and output of which are connected respectively to the output of the source of trigger pulses and the triggering input of the timer, the first input of each element I The first input of the first element I is connected to the blocking node, the second input of each element I and the clock input of the timer are connected to the output of the clock generator, the control input of which is connected chen output to the clock timer, the outputs of memory elements are connected to the input of the codes and to direct input node blokirOBki inverse input connected to the output of the last memory element.

This allows you to increase the reliability of the device during the formation of complex control programs.

The drawing shows a block diagram of the proposed device. It contains a source of 1 triggering pulses, a blocking unit 2, a timer 3, a driver of 4 clock pulses, elements 5i, 5u, ..., 5n, and elements B1, bg, ..., 6ts.pam, inverse control circuit 7, a driver 8 codes with output control circuits 9 and a correction unit 10.

The device for software control works as follows.

The source 1 of the triggering pulses produces single pulses with a follow-up period T. When the triggering pulse arrives at the interlock unit 2, the latter connects a direct current source with voltage Ец to timer 3 and sends a signal to the first input of the first element 5i I. From this moment, timer 3 starts to work out the time interval D tj of the first cycle, while the power supply circuit of the timer and the entire device is blocked and remains connected for the entire time of the cycle Ti, consisting of n intervals corresponding to the n cycles of operation of the device properties.

After processing the first interval D ti at time t, timer 3 sends a signal to the 4 clock pulse shaper, which generates a pulse signal of short duration and sends it to all elements 5), 5s, ..., 5n I and to the clock input of timer 3 , carried out feedback and prepared it for processing the next interval. After that, the first memory element 6i is triggered, since the first input of the first element 5i And the potential signal arrived earlier from block 2, and the second input received a pulse clock signal from the former 4 and, therefore, at the moment of the last output element 5i And the signal arrived at the input element b | memory

Further, the signal from the output of the memory element 6i enters simultaneously to block 2, which leads to memorization of the fact that the first clock was tested at an interval of D ti for the entire time of the working cycle Tts of the device, into timer 3, which leads to switching the time of its master circuits, the code generation unit 8, which leads to a change in the states of the elements of the encoder, and to the first input of the next element 51. And, which prepares it to pass the next clock pulse to the input of the element 6.

Then, the next Atj interval is started by timer 3, and after it has been switched, the switching process is repeated as described by Bbioje, i.e. at time tj, timer 3 is sent to shaper 4 and, as a short pulse, goes to elements 5, after which just one more

element 6,. memory, which leads to memorization of the previous clock, switching the time of the driver circuits in timer 3, changing the state of the elements in the shaper 8 codes and preparing the next element 5 "l. And passing the pulse signal from shaper 4 to the next element). memory

The process of working out time intervals and memorizing preceding clock cycles repeats automatically until

after working off the last interval it from the output of the 5pI element, there will be no signal to the last element of 6p.pam. This results in an inverse signal from element 6p. Along circuit 7 to block 2, which disconnects the power source from timer 3 and all memory elements 6. The entire device, except for the code generator 8, is de-energized and returns to its original state, and the accumulated information in the memory elements 6 is erased.

The entire process of testing the control program is repeated only in the case of receipt of the next triggering pulse from the source 1 of the triggering pulses at the blocking unit 2.

Correction block 10 is used if the timing parameters of switching elements 5 and b are very different. Using the correction unit 10, the time constant of the chains of timer 3 is changed and thereby the duration of the pulse signal from the former 4 to the elements 5 is changed. The range of possible increase in the duration of the clock pulse is 100% and its optimal value is 50% of the original nominal value.

The outputs 9 of the driver codes 8 serve to control the operation of actuators. Memory elements 6 may

 used as control elements, while from outputs 9 with indices from 1 to n, control signals will be taken, with the help of which a control program with a redundant code of the form - 1 is implemented, for example, for n ± 5 numerical value: 3-7-15-31-63, and when using the shaper elements of 8 codes from outputs 9 with indices from n -f 1 to m, control signals are removed that implement more complex control programs and, in particular, programs with overlapping and skipping separate cycles depending on the parity and oddness of the post captive firing pulses and t. d.

Claims (1)

Claim A device for program control, containing AND elements, the output of each of which is connected to the input of the corresponding gj memory element, a code generator, a trigger pulse source, a clock pulse generator and a timer, characterized in that, in order to increase the reliability of the device, it is introduced blocking node, the trigger input and output of which are connected respectively to the output of the trigger pulse source and the trigger timer input, the first input of each AND element, except the first, is connected to the previous output of the first memory element, the first input of the first AND element is connected 5 to the blocking unit, the second input of each And element and the clock input of the timer are connected to the output of the clock generator, the control input of which is connected to the clock output of the timer, the outputs of the memory elements are connected to the inputs of the code generator and to the direct inputs of the lock node, the inverse input of which is connected to the output of the last memory element.