SU720711A2 - Delay unit - Google Patents

Description

I

The invention relates to instrumental engineering and can be used in signal recorders, stroboscopic transducers, etc.

Delays are known that contain a pulse generator, a coincidence element, a counter, a first trigger, a third trigger, a current generator, a capacitor, a key element, a threshold stage 1.

} The disadvantages of this device are the relatively large discreteness of the delayed input signal, as well as the inconvenience of its operation due to the incompatibility1 between the value of the generated delay and the control code of your counter, since the resulting delay also includes the time of sawtooth formation.

The purpose of the invention is to reduce the step of discreteness of the input signal delay.

With this goal in the device, containing the gun fuel pulse, soy; 1INNIIII through the coincidence element with the counter, the first trigger, whose output through the coincidence element is connected to the input of the second trigger, the other input of which is connected to the output of the counter, and the output from the control input of the current generator connected to the condensator, the key element and the threshold cascade The control input of the key element is connected to the output of the first trigger, and the output of the threshold cascade is connected to the input of the first trigger, a digital-to-analog converter, a subtraction unit and a group of gates are entered. subtracting unit moves through the respective valves are connected with the control input of the counter; The transfer output of the subtraction unit is connected to the second inputs of the valves and to the input of the higher bit of the analog converter, the output of which is connected to the second input of the threshold stage, the inputs of the subtraction unit and the inputs of the converter, except for the input of the high bit, i ng, I, I, I, I will use the current signal; delays. The introduction of these blocks allows you to control the threshold for the operation of the horn cascade. Due to this, comparing with known devices, the proposed device provides a smaller discrete step, which is determined by the width of the digital-to-analog converter and the parameters of the keys. FIG. 1 is a schematic diagram of the device; FIG. 2 shows timing diagrams explaining the operation of the device. The device contains a pulse generator 1, a coincidence element 2, a counter first trigger 4, a second trigger 5, a current generator 6, a capacitor 7, a key element 8, a threshold stage 9, a digital-to-analog converter 10, block 1

subtractions, valves 12.

The device works as follows. . .

 The input signal (Fig. 2a) overturns the -trigger 4 (Fig. 26) and due to the opening of the key element 8, the formation of the sawtooth voltage on the power supply 7 starts due to the current from the generator b (Fig. 2c). At the moment of arrival of the next pulse from generator 1 (Fig. 2d), trigger 5 (Fig. 2d) overturns, which interrupts the formation of sawtooth voltage on the capacitor 7 and counter 3 calculates the pulses of generator 1 of the value corresponding to the code at the outputs of the gates 12. Impulse on counter 3 returns the trigger 5 to the initial 6 state and the formation of the saw-tooth voltage continues until the voltage (current) equality reaches

..-- -: -. ,, .... -.-.-- bypassing the threshold cascade 9 when the output signal of the device is formed and the trigger 4 returns from its initial state (Fig. 26). Block 11 subtracts one from the integer period. In this case, the total duration of the sawtooth voltage does not exceed two oscillation periods of generator 1, the first of which relates to synchronization, and the second to delay by a value specified at the input of the digital-to-analogue converter 10. In the case of counter 3 & HI, a zero code arrives, which provides a switchable state of trigger 5 and an unbroken fork for sawtooth voltage iaa capacitor 7. In particular, for l 1

code and actual latency due to sawtooth voltage.

The minimum delay resolution of the proposed device is determined by

the leakage current of the capacitor 7 when the key element 8 is open and the current generator 6 is turned off. It can be shown that the minimum discreteness of the delay dT in the invention is determined from the condition L where the charge current of the capacitor 7; D is the leakage current of the capacitor 7; T is the oscillation period of the generator 1.

If there is a repeater in the circuit of the threshold cascade on the field toanzistor, it is possible to get the ratio - S, which allows to reduce the discreteness of the time interval (delay) of the proposed device by 2-3 orders of magnitude compared to the known analogue devices.

Claims (1)

Invention Formula Delay device auth. St. USSR No. 560331, characterized in that, in order to reduce the discreteness step of setting the input signal delay, a digital-to-analog converter for reading and a group of gates are added to it, while the outputs of the reading module are connected to the control inputs of the counter through the corresponding valves to the second inputs of the gates and to the input of the higher bit of the digital-to-analog converter, when there is no signal at the output of the transfer of the subtraction unit 11, the value of the higher bit of the lifroan The second converter 10 is equal to 1 and a saw section is used that corresponds to a delay of 1-2 oscillation periods of the generator 1. If, however, 0, then the zero transfer code is fed to the input of the counter 3, as before, and the output the digital-to-analog converter 10 is equal to 1, and a saw section is used corresponding to a delay of 1-2 periods of oscillation of the generator 1. Thus, the proposed device forms time intervals with low discreteness. At the same time, the disadvantage of the known device is eliminated, the mismatch for 1 period of oscillation of the generator 1 between the control 5 720711 The fibixon of which is connected to the second in the S-hospital of the threshold cascade, the block inputs taken into account during the examination power supply and inputs of an analogue converter, except for the higher input pav- -1. USSR copyright certificates p yes, connected to the terminals set 56O331, cl. H 03 K 5/153, delays. 02.22.75 (prototype). Source Information, Into installation I IzaE r m / h I f ten Qbixod ifepe, .-. i ,. . 2 720711