SU717780A1 - Fourier coefficient computing arrangement - Google Patents

Description

The invention relates to the field of computer technology and can be used in digital equipment for spectral analysis of radio engineering and acoustic signals, in high-speed digital filters, devices ⁵ for calculating correlations and for calculating Fourier coefficients. A device is known in which the task of increasing speed is solved by calculating partial sums on four processors 1.

However, such a technical solution makes it possible to increase speed only by a factor of 4 due to a proportional increase in the volume of equipment. Όρό Moreover, the computation speed is limited in this device by the speed of random access memory.

The closest technical solution to this proposal is _m unit for calculating the Fourier coefficients, comprising analog-to-digital converter having an information input connected with the input device control - with the output of the first genepamyati where N - number of Fourier coefficients, the constant storing unit, which is connected to the input with the first output of the control unit, the output with the first group of inputs of the arithmetic unit [2 J.

This device has a memory consisting of blocks of shift registers. The first block consists of K parallel-connected shift registers with a bit capacity. each (K-digit capacity of numbers). The second - of two subunits containing K registers with a capacity of -j- bits, etc. The last block contains N subunits of K single-bit registers. The arithmetic device of the calculator 'has a distributed structure and is divided into EofMarithmetic devices (AU), each of which serves one memory block, moreover, the operand from the output and input of the corresponding memory block is fed to the inputs of each AU

4717780 value of the rotation vector stored in read-only memory (ROM). The choice of the required value of the rotation vector is carried out using the control device. The shift of information in the registers occurs with the frequency of the analog-to-digital converter (ADC) when applying to all the pulse registers the clock generator (TG) of the ADC.

The principle of operation of the calculator provides that during the first clock cycles of the TG, when the first memory block is filled, all AU blocks are inactive / further, during - ^ - clock cycles only the first AU block works, processing the samples contained in the first memory block. Then, during the -g- cycles, the first and second blocks of the distributed AU work, etc. All AU blocks work only in the interval between samples of the input implementation with numbers N - 1 and H. Moreover, on this interval AU performs about N operations of multiplication and addition of complex numbers, which limits the speed of the device in real time and requires significant hardware costs. Thus, a disadvantage of the known device is the lack of speed and a significant amount of equipment. ''

The purpose of the invention is ’to eliminate these drawbacks, to increase performance.

The purpose of the invention is achieved in that the device comprises a second pulse generator, first and second switches, a group of buffer registers / first and second switches and a decoder, and the output of the second pulse generator is connected to the first inputs of the first and second switch and the first control input of the arithmetic unit, the second input the first switch is connected to the output of the first pulse generator, the output to the control input of a group of buffer registers, information input of which is connected to the analog output level converter, the output of the group of buffer registers is connected to the input of the first memory register, the control input of which is connected to the output of the second switch, the second input of which is connected to the first output of the decoder, the outputs of the memory registers are connected to the inputs of the first switch, the control input of which is connected to the second output of the block control, the third and fourth outputs of which are connected respectively to the control inputs of the decoder and the second switch, the input of the control unit is connected to the first output ari meticheskogo unit, the second output of which is connected to the input of the second switch, the outputs of which are connected to the I control inputs of memory registers group information inputs of which are connected to the outputs of the decoder.

The block diagram of the device for calculating the Fourier coefficients is given in the drawing. The device contains groups of memory registers 1, the information input of the device! - 2, read-only memory (PZB) -.3, control unit-4, analog-to-digital converter ¹ repeater (ADP) - 5, first pulse generator 6, group of buffer registers - 7, switches 8, 9, arithmetic unit 10, switches 11, 12, decoder 13, pulse generator 14.

The group of buffer registers 7 and the first group of memory registers 1 have the number of registers ’equal to the number of bits of the code at the ADP output. The second group of memory registers 1 has two groups of registers, each of which also contains the number of registers equal to the ADC bit. In the third block of such groups - four, in the fourth 8, etc.

The length of the buffer registers and registers of the first memory block is N bits, and in the registers of the first block there is a tap from the cell with the number ^. The length of the registers of the second block of the third is -u, etc.

The device operates as follows. The input implementation in analog form ^{- is} continuously fed to the input of the ADC 5. From the output of the ADC 5, discrete samples with a frequency of the first clock 6 in parallel code are loaded into the buffer registers, switch 8 depreciates the supply of signals from the first clock 6 to the synchronizing input of the buffer register group 7. At the moment when the count with the number S is received at the input of the buffer register group, switches 8 and 9 are activated and the synchronizing inputs of the buffer register block of the first memory block are connected to the output of the second clock generator 14, the frequency of which is selected so that in the pause between the last count of the previous implementation and the first count of the next implementation, the contents of the group of buffer registers 7 are transferred to the first memory register 1. After that, switch 8 reconnects the synchronization inputs of the block of buffer registers 7 to the output of the clock generator and this unit is ready to receive from the ADC samples of the next implementation. At the same time, the switch 9 connects the synchronizing inputs of the first block of memory registers 1 to the output of the decoder 13, and the control unit generates the address of the switch and the safety control module corresponding to the first operands for calculation. At the first stage of calculations, the address of the switch corresponds to the outputs of the first block of memory registers and taps from their cells with numbers. These operands are fed through a switch 11 to the inputs of the AU, which, with a high speed due to the frequency of the generator 14, performs the standard operation of multiplying one of the operands by the rotation vector and adding the product to the other operand. After performing the standard operation, a control pulse (IU) is generated at the synchronizing output of AU 10, signaling that the AU is ready for the next operation. By the action of this pulse, the AU generates the multiplexer address corresponding to the inputs of the memory register block and the address of the decoder 13, from the output of which a shift signal is supplied to the registers of the second ~ this way, as a result of the block calculations. At the same time, the address of the switch is the address of the decoder for shifting information in the first memory block 1. After that, operands are received at the input of the arithmetic block 10 to perform the following standard operation. The described procedure is performed once until the registers of the second memory block are full. After that, AU similarly performs operations with data contained in the first and second memory blocks, removing the corresponding 7 operands from the inputs and outputs of the registers. In this case, the result of the standard operation on the data of the first block is entered into the second block, displacing the operands stored in it, which, in turn, enter the arithmetic block, and the memory block. The tabs are entered by the rearithmetic control unit (4); Ni PPZ 3 forms, as well as ^{6, the} result of the calculations above them is entered in the third block. After NEo ^ N integrations, the registers of the last block of pa-, five contain N Fourier coefficients, which can be sequentially extracted with a generator frequency of 14 for a time equal to the pause between samples of the input implementation. When choosing an element base providing a multiplication time of the order of 200 ns. The described device is capable of real-time Fourier transforms from 1024 points in a time of the order of 2 ms. In order to get such a speed in a prototype device, with equal complexity of the arithmetic device, it is necessary to use elements that less than provide the time of multiplication ns, or in proportion to the volume of the equipment in A U.

invention mule

Claims (2)

1. USSR author's certificate No. 421994, cl. & 06 F 15/34, 19J71. 2. US patent number 3816729. class. 235-156 from 11.06.74 xfc SfS: i ffl :; S -a ": ass:: 9B