SU711578A2 - Arrangement for computing exponential function - Google Patents

Description

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  The invention relates to the field of digital computing and can be used to implement hardware for calculating the exponential function and its square.

A device is known for calculating an exponential function from an author. 538366, containing a control unit, the outputs of which are connected to the control inputs of the cumulative and shift registers and the input of the one-way memory block, the outputs of the cumulative registers are connected to the inputs of single-digit adders-subtractors, the outputs of which are connected to the inputs of the cumulative registers, the output of one storing register is connected with the input of the pseudo-part determination unit, the output of which is connected to the control input of one of the one-bit adders-subtractors, the device also contains a repeater unit No operations, a reset unit, a convergence analysis unit, gates, one inputs of which are connected to the output of a pseudo-part determination unit, other inputs of which are connected

with the outputs of the one-way memory unit, and the outputs of the valves are connected to the input of a one-bit totalizer, the input of the convergence analysis block is connected to the output of the corresponding cumulative register, and the output is connected to the input of the reset unit, the output of which is connected to one input of the control unit; the output of which is connected to the repeating unit 1,

Its disadvantage is the impossibility of calculating the square of the exponential function. The purpose of the shadow invention is to make it possible to calculate the square of the exponential function. The goal is achieved in that the device contains third and fourth adders, subtracters,

0 a shift unit and a third cumulative register, the first output of which is connected to the first input of the third adder-subtractor, the output of which is connected to the first input of the third storage register, the second input of which is connected to the sixth output house of the control unit, the seventh output of which is connected to the first input shear block, informational inputs are

They are connected to the information outputs of the IKhtselny register, the outputs of the shift block are connected to the first and second inputs-1 of the fourth cyiMMa-subtractor, the third input of which is connected to the output of the enax determination unit, the output to the second input of the third totalizer-subtractor.

The drawing shows a block diagram of a device for calculating an exponential function.

Device Contains single-digit combiners 1-4 combinational type, cumulative registers 5-7, shift register 8, shift block 9, made, for example, on two Shift registers, block of one-sided memory 10, made with random, sampling of two constants 6i (1 + 2 Mi 2l. (1-2). At the same time, elements 11-12, a sign determining unit 13, made in the form of a trigger and logic elements, convergence analysis unit 14, made in the form of a digital comparison circuit, a reset unit 15 made in the form of a trigger and logical elements iteration block 16, made in the form of a counter and logic elements, control unit 17 consists of clock generator, counters, logic elements, etc. The output of the device is the input of the first accumulative 5 Egr 5, the output of the device is exponential function in the input of the second cumulative pegister, 6 for the square of the exponential function - the output of the third cumulative register 7,

The calculation of the exponential function and its square in the proposed device for the interval of variation of the argument is based on a parallel solution in the iterative process of difference recurrence relations, for example, for a binary number system:

Z, -X 2j - «« (l (j-2 -) Z, 0

n Sirrn 7- - J + 1 with „, t-1 npHZj 0 J-o / i--

    +. n / x

e

Uo-1 Uj, yi i-Uj + c j.Uj.2-VUj.2

: Un-e "

Each recurrence relation is calculated sequentially in (n + m cycles, where n is the number of argument bits, m is the number of additional (protective) bits dn of offset offset during the shift. Since the system functions W (;; does not satisfy the condition m convergence. (correctability iterations) for numbers

operator

.i-i :.

 (i-2) 2.en ()

5 (,, e. {V2TO) to avoid occurrence of convergence on the interval of argument change, it is necessary and sufficient to repeat twice all iterations, either only 3,5,7, etc. iterations, or 4,, 16 and so on. e. In subsequent cases, the computation time is reduced.

In the initial state, the accumulative register 5 is entered in the specified argument X; cumulative registers 6-7, the shift register 8 and the shift block 9 are set to one state.

Calculations in any j -th iterations in the described device are performed as follows

From the outputs of the control unit 17, pulses are output for svdig contents in the shift register 8 and the shift block 9, then a series (sequence) of clock pulses is fed to advance the contents of the storage and shift registers 5-8, the shift block 9 and the next constant

& 1 (l + (: j, .. 2O-1-0 from one-way memory 10) to the corresponding inputs of subtractors-subtractors 1-4 From the output of the shift register 8 to the second input of the adder-subtractor 2, the value of y- 2 is applied. the second output of the third cumulative register 7 to the first input of the shift block 9 is supplied the value

(Jj, from the first output of the shift block 9 to the first input of the adder-calculator 4, the value Uj 2 v is fed, from the second output to the second input - the value Uj 2 i The algebraic sum of these values is fed to the second input of the adder-subtractor 3. The results are algebraic summation-subtraction from the outputs of totalizers of emitters 1-3 is entered by younger bits forward into the shear-freed high bits of accumulative registers 5-7 and advancing to their beginning. After the iteration has ended, accumulative registers 5-7 contain intermediate results s that are transferred from cumulative register b to the shift register 8, and from cumulative register 7 to the shift block 9. By the sign of the content of cumulative register 5 in the sign determining unit 43, a signal is generated O: + i with a positive content of cumulative register 5, or QJ -J when the accumulative register 5 is negative. In the first case, totalizer 1) s-subtractors, 2 and 4 operate in addition mode on the second inputs, and from the one-sided memory block 10, through element 11 of the second input of adder-subtractor 1 the constant en is supplied ({ ). in the second case, the adders-subtractors 2 and 4 operate in the subtraction mode, and the adder-subtractor 1 is supplied, and the element And 12 constant rf (-24 i /.

The calculations in the following iterations occur in a similar way.

The iteration repetition block 16 does not change the iteration number j following the iterations. In the repeated iteration, the previous constant is involved (taking into account the new value of the operator a, -, the values of Vj and Uj are shifted by the previous number of bits.

After (n + 1) iterations, or when the content of accumulative register 5 is equal to zero (in the latter case, the stop signal is output from the output of convergence analysis block 14 via reset unit 15 to control unit 17 and the latter stops issuing clock pulses at the next iteration) finished. In cumulative

Register B contains the value of the exponential function (e); in Cumulative Register 7, the value of the square of the exponential function ().

The table shows a specific 5 numeric example of calculating the exponential function and its square for the eleven bits of the dargo argument, 001953125. The table successively shows the iteration number, its 0 weight, the contents of the cumulative register 5, the value of the operator for the given (+ 0 and iteration, the value of the next constant supplied to the adder-subtractor 1, the generation of cumulative register 6 and

the contents of the cumulative register 7. The exact values of the calculated functions are equal to:

X2x

e 1.001955 and e 1.003913822. 0 Calculation errors are 4U -o, 000084 and 4f -0.000096701. The table also demonstrates that, at the tenth iteration, the contents of cumulative register 5 is less than the value of the twelfth bit and the calculation process can be completed, with the error D V 0.000165.

Claims (1)

1. USSR author's certificate No. 538366, class C. 06 F 15/20 from 1973.