SU696505A1 - Multichannel pulse counter - Google Patents

Description

one

The invention relates to a device for cy phyla metering of electricity generated by several units.

A device for total metering of energy consumption by an enterprise is known, consisting of three transformer sensors included in different phases of the same source. Pulse counters with integrated sensors are connected to one of the control inputs of the first trigger, the output of which is connected to one of the outputs of the element I, and the other of its input is connected to the output of the pulse generator, and the output through the second trigger to the second control input of the first trigger. The adder is made with one common input to which the outputs of all elements And 1} are connected.

Accounting for the load is based on the principle of sequential counting the number of revolutions of the electric meter disk. This device cannot be used to calculate electricity from different objects, where signals can come independently from one another, partially or simultaneously coincide since the known device operates from the same source, where the phases are shifted through an angle of 120

The closest technical solution is a device containing an OR element, the output of which is connected to the input of a pulse count indicator and in each channel a memory element, the first input of which is connected to the corresponding counter input, the first output of the memory element connected to the first input of the first AND element , the second output is connected to the second input of the first element I and to the first 5 input of the second element I of the subsequent channel 2.

five

A disadvantage of the known device is its low accuracy.

The purpose of the present invention is to improve the accuracy of the counter. For

0 this element is NOT entered into each channel of the counter, the differential circuit is a delay element, the input of the element is NOT connected to the corresponding input of the counter, the output of the element is NOT connected to the third input of the first AND element and to the second input of the second And element, the output of which is connected through the delay element with the second input of the memory element and directly connected to the third input of the second element And the subsequent channel, the output of the first element I is connected to the input of the differentiating circuit, the output of which is connected to the fourth input of the second element AND with the corresponding input of the element OR. In the drawing isobrosoken proposes a counter.

The proposed counter contains inputs 1, 2, 3, 4 channels, elements NOT 5 b, 7, 8, elements 9, 10, 11 and 12 of the memory (triggers) with unit 13, 14, 15, 16 and zero 17, 18, 19, 20 outputs, elements And 21, 22, 23, 24 and 25, 26, 27, 28, connected to the second inputs of the flip-flops, differentiating circuits 29, 30, 31, 32, element OR 33 with an indicator 34 of the pulse counting elements 35, 36, 37, 38 delays, made for example in the form of capacitors.

The proposed meter works barely.

From the leading edge of the input impulses arriving at the inputs 1, 2, 3, 4, the flip-flops 9, 10, 1b, 12 are transferred from the zero to the one state, and elements 21, 22, 23, 24 are prepared for work. Zero outputs of triggers prohibit the operation of elements And the subsequent discharge.

During the operation of the counter, the following characteristic situations occur.

The pulses arriving at the inputs 1, 2, 3, 4 from the sensors do not coincide in time with one another.

From the leading edge of the input pulses, the flip-flops 9, 10, 11, 12 from the zero to one state are transferred. For example, at input 2, a pulse is applied that pushes trigger 10 into a single state and prepares the AND 22 element for operation.

Since the trigger 9 is in the idle state, then from its output 13, the element 22 and 26 receives a single signal. The output of the element NOT b the elements 22 and 26 are blocked for the duration of the input pulse. When the input 2 from terminal 2 disappears through the NOT 6 element, the ban on AND 22, 26 elements is removed. And 22 is activated and the Differential Circuit 30 is triggered. Since the output signal of the AND 26 element is delayed by the clamping element 36, the output signal from element 26 is absent element 22 and the triggering of circuit 30. Differentiating circuit 30 bans the element 26 and the element OR 33 impulses the pulse to indicator 34 for registration. After the operation of the differentiating circuit 30, the prohibition from the AND element 26 is removed and it issues a signal to flip the trigger 10 to zero, its position. The latter allows the operation of the elements And 23, 27, In addition, the pulses arriving at the inputs 1, 2, 3, 4, coincide in time.

From the leading edge of the pulses from the inputs 1, 2, 3, 4, the flip-flops 9, 10, 11, 12 are transferred from the zero to one state. On the element And 21, 22, 23, 24 and 25, 26, 27, 28 with the flip-flops 9, 10, 11, 12 zero outputs 17, 18, 19 postuga; prohibition. On the element And 21 from the output 17 of the trigger 9 nocTyneiST single signal. Element And 21 is prepared for work. When input i; vshylca disappears at input 1, element I 21 triggers and differentiation circuit 29 prohibits the positive positive signal that arrives at element 25, and through element OR 33 it registers with indicator 34. JpiH eliminating false triggering of trigger 9 along the circuit element HE, element And 25, when due to the final sign of the element response time And 21 it is possible for the trigger 9 to interfere with the input of setting it to the inoperative position, the signal from the output of the And 25 element is fed through the delay element 35. After. the operation of the differentiating chain 29 of the prohibition of the AND 25 element is removed and it sends out through the delay element 35 a signal to re-flip the trigger 9 to the Egle position, and from output 13 a single signal arrives at the elements 22,26, removing the prohibition from them. If, at input 2, the signal is gone, then element 22 causes the signal for triggering differentiating circuit 30, which is positive. Pulse bans the element 26 and impulses, and through element OR 33 it outputs a signal to identifier 34 for registration. After the operation of the differentiating circuit 30, the prohibition on the AND 26 element is removed and the trigger-10 is released over time, as determined; element 38 of delay 36 to the inoperative position. From output 14, a single signal is sent to elements AND 23, 27, which removes the prohibition from them, and, if input signal 3 disappears, then element 23 produces a signal to trigger differentiating circuit 31, which outputs the ban on the element And 27, and through the element OR 33 issues a signal to the indicator 34 for registration. After the operation of the differentiating circuit 31, the element 27 is removed and the trigger moves to the zero position.

The operation of the fourth channel is similar to that described for the second and third channels.

Claims (2)

1. Authors certificate of the USSR 463998, cl. G 06 M 3/08, 1973, 2. USSR author's certificate No. 370622f Clo G 06 M 3/08, 1969.