SU763806A1 - Instantaneous frequency meter - Google Patents

Description

.

-.

2

The invention relates to a measurement technique and is designed to measure digitally the frequency of the treatment of electrical pulses.

A digital frequency counter is known about the functional coding of the time interval, which contains a subtracting counter, an approximator that divides the reference frequency. In the frequency counter, occurs parallel to the process of quantization of period 1.

The disadvantage of the known frequency meter is the need for a high reference frequency in order to obtain the required measurement accuracy, since a frequency divider with a large division factor is used in the approximator.

A frequency meter is known in which the conversion is carried out after the quantization process of the period T2.

A disadvantage of the known device is the low speed of the device, since the measurement result of the instantaneous frequency value is obtained

control, and the second input of the block: control is connected to the input of a constant number counter.

FIG. 1 is a block diagram of the instantaneous frequency meter; in fig. 2 - functional block diagram.

The frequency meter contains (Fig. 1) a period measurement unit 1 with shaper 2 included in it, a reference frequency generator 3, an AND 4 element, a range selection unit 5, an hLf 6 counter, a delay element 7, and a group of elements AND 8, a control unit 9, a constant number counter NC 10, a frequency counter 11.

At the beginning of the measurement, the initial value of the frequency Hp is set in the counter of frequency 11, the counter code of the number N-p is set in the counter NT 6. , the block selection range 5 includes the first range. At the same moment, at the output of the imaging unit 2, an enabling signal appears at the first input of the element AND 4. The pulses of the reference frequency generator 3 arrive at the second input of the element 4, pass further to the input of the range selector 5 and, since the first range, these impulses with a frequency of FO arrive at the counting input of counter 6. As the pulses arrive at counter 6, the output of a group of elements AND 8 (output of a binary multiplier) produces pulses that enter the input of control unit 9.

The control unit 9 (Fig. 2) operates as follows. When a pulse arrives at its input from the output of a group of elements AND 8 from the output of the control unit 9, a pulse arrives at the subtracting input of the counter 11. With a minimum delay relative to this pulse, a pulse is sent to the summing input of counter 11 from another output of the control unit. At the same time, the presence of a pulse at the output of a group of elements And 8 is controlled at the input of the control unit 9 in response to the incoming signal from the output of counter 11. If the pulse is not The output of this group of elements, And 8, is, then a pulse from the output of the control unit 9 to the subtracting input of the counter b again arrives, the value of the number (FX frequency) in the counter b is reduced by one. If there is no pulse at the input of the group of elements And 8, then from the output of the control unit 9, two inputs arrive at the readout of counter 6: pulses, the value of the number in counter 6 (frequency F) decreases by two units. After that, the control unit 9 is in the standby mode - until the next pulse from the output of the group of elements AND 8 (binary multiplier).

The operation of the control unit 9 is as follows. Upon the Initial Setup command (the buses of this command are not shown in Figure 2) the counter 10 is zeroed, the triggers 12, 13, 14. The output of the trigger 14 is given a prohibition signal for the element 19, and the output of the trigger 12 is given permission for the element 16, from the trigger

13, permission is given to the element AND 18. The capacity of the counter 10 is equal to the number C, and C const. From the moment of the removal of the Initial Setup command on the input of the control unit 9, i.e., to the input of the And 19 element, pulses from the output of the And 8 group of elements (i.e., from the binary multiplier output) begin to arrive. Through the element And 19 these pulses do not pass, because

at the second input of the element AND 19, the prohibition signal from the trigger 14. The pulses from the output of the group of elements AND 8 also enter the input of the counter 10, in which they are counted. As soon as the number of these pulses becomes equal to number C, the counter 10 will overflow, and the overflow pulse from the output of counter 10 will set trigger 14 to state 1. Note here that when the next pulses are received from the output of the group of elements And 8, counter 10 may overflow several times, however, overflow pulses from the output of this counter, arriving at the single input of the trigger 14, cannot change the state of the trigger 14. So trigger

14 is in state 1 after the arrival of pulses from the output of the group of elements AND 8 to the input of the control unit 9. Thereby, from the output of the trigger 14 to the second input of the element AND 19 the resolution is applied, and (c + 1) -th, (C + 2) - nd etc. pulses from the output of a group of elements and 8 pass through the element AND 19 to the input of the element AND 16

and to the input element AND 17. -When a (C + 1) -th pulse arrives from the output of a group of elements AND 8, the latter passes through the element AND 19 to the input of element AND 16, at the output of which a signal is input to the input of trigger 12. Rear the front of this signal (pulse) trigger 12 is set to 1, the signal from the output of this trigger prevents the passage of subsequent pulses through the element AND 16. From the output of the element AND 16 (C + 1) -th pulse also goes to the first input of the element OR

15 and the input of the delay element 20. From the output of the element AND 16 (s + 1) -th pulse is also fed to the first input of the element OR 15 and to the input of the delay element 20. From the output of the element OR 15 the pulse goes to the subtracting input of the counter 11. From the output delay element 20 pulse is fed to the summing input of the counter 11, and

also on the element And 17 and on the delay element 21. If at this moment the second input of the element And 17 comes from the output of the element And 19 (i.e. from the output of the group of elements And 8), then the trigger 13 will receive a signal that sets the trigger 13 to 1. If, at this moment, there is no pulse at the second input of the element And 17, then the trigger 13 will remain in the initial O state. With a delay relative to the pulse from the output of the delay element 20, a pulse is formed — at the output of the delay element 21, this pulse goes through the OR element 15 to the subtracting input of the counter 6 and to the input of the delay element 22, from the output of which the pulse goes to the second input of the element 18. Depending on the state of trigger 13, this pulse passes (if trigger 13 to O) or does not pass (trigger 13 to 1) to the input of the OR 15 element and, respectively, to the subtracting input of counter 6. This same pulse goes to the zeroing inputs of the trigger 12 and 13, Return ascha their original ON state. The operation of the control unit 9 when a subsequent pulse arrives at its input from the output of a group of elements And 8 is similar to the block described above when the (C + 1) -th pulse arrives.

At the moment when the pulses arrive at the input of the counter 6, an overflow pulse is generated at the output of the counter 6. This pulse triggers delay element 7, and in j, counter 6 sets the number -j.

At the same time, the overflow pulse from the output of the counter 6 is fed to the range selection unit 5, and the range selection unit 5 continues to operate in the first range. From the generator, frequency 3, through the element 4 and the block of selection 5 on the counting input of the counter 6 continue to receive pulses with a frequency f. After the next pulse at the input of the counter 6, from the output of the group of elements I 8, a pulse will arrive at the input of the control unit 9.

It should be noted that, by the Start Setup command, a number corresponding to the maximum frequency value is set in the counter 11. If the counter 6 overflows during the measurement time, it means that the frequency at the input of the frequency meter exceeds the maximum allowable value measured by the frequency meter.

At the end of the period T of the frequency F at the input of the imager 2, from the output of the imager 2 to the input of the element 4, a prohibition signal is received, and the value of the frequency F with the accuracy tl of the least significant bit is removed from the discharge outputs of the counter 6.

The technical and economic effect of the proposed invention is to increase the speed with

frequency measurement. In fact, the proposed instantaneous frequency frequency meter has a maximum speed, since it allows obtaining the frequency value with the required accuracy at the moment of the end of the first period of the measured frequency.

Claims (1)

Invention Formula An instantaneous frequency meter containing a period quantizer consisting of a reference frequency generator and an input driver, the outputs of which are connected via a match element to an automatic range unit, the second input of which is connected to the output of a period number counter and through an element of a jumper to the installation input of a period number counter, whose counting input is connected to the output of an automatic range unit, first and second groups of inputs of which are connected respectively to the outputs of frequency counters and the number of periods, and the output is connected to the input of a constant number counter whose output is connected with the first input of the control unit, q distinguished by the fact that, in order to improve speed, the frequency counter is reversible, the total number of which and subtracting inputs are connected respectively to the outputs of the control unit, and the second input of the control unit is connected to the input of a constant number counter. fx BMWnrouffOt- tx. etfffMifM Cui f v yHmt- 9x evfnfVMffS С Stxo cf f group ajtefeffmofffe S iifpffo cfem ifffty 0