SU684709A1

SU684709A1 - Discrete frequency multiplier

Info

Publication number: SU684709A1
Application number: SU772474450A
Authority: SU
Inventors: Юрий Николаевич Цыбин
Original assignee: Ленинградский Ордена Ленина Электротехнический Институт Им. В.И.Ульянова /Ленина/
Priority date: 1977-04-18
Filing date: 1977-04-18
Publication date: 1979-09-05

Description

1one

Изобретение относитс к радиотехнике и может использоватьс дл расширени диапазона измерени частотомеров в области низких частот.The invention relates to radio engineering and can be used to extend the measurement range of frequency meters in the low frequency region.

Известен дискретный умножитель частоты, содержащий последовательно соединенные генератор первой опорной частоты, первый счетчик, устройство пам ти, устройство уравнени и буферное устройство, а также последовательно соединенные генератор второй опорной частоты и второй счетчик, выход которого подключен к другому входу устройства сравнени , а установочный вход первого счетчика соединен с установочным входом устройства пам ти 1.A discrete frequency multiplier is known that contains a first reference frequency generator, a first counter, a memory device, an equation device and a buffer device, as well as a second reference frequency generator connected in series, and a second counter, the output of which is connected to another input of the comparator, and the setup input the first counter is connected to the installation input of the memory device 1.

Однако этот дискретный умножител частоты обладает недостаточной точностью умножени .However, this discrete frequency multiplier has insufficient multiplication accuracy.

Цель изобретени - повышение точности умножени путем обеспечени синхронизации выходного сигнала вхоHtJM сигналом.The purpose of the invention is to increase the multiplication accuracy by ensuring the output signal is synchronized with the HTJM input signal.

Дл этого в дискретный умножител частоты, содержащийпоследовательно соединенные генератор первой опорной частоты, первый счетчик, устройство пам ти, устройство сравнени и буферное устройство, а также последвательно соединенные генератор второй опорной частоты и второй счетчик, выход которого подключен к другому входу устройства сравнени , а установочный вход первого счетчика соединен с установочным входом устройства пам ти, введены последовательно соединенные устройство дифференцировани и элемент ИЛИ, To do this, the discrete frequency multiplier, which contains the first reference frequency generator, the first counter, the memory device, the comparison device and the buffer device, as well as the second reference frequency generator and the second counter, the output of which is connected to another input of the comparison device and the the input of the first counter is connected to the installation input of the memory device, the differentiation device and the OR element are connected in series,

0 другой вход которого подключен к выходу буферного устройства, а выход подключен к установочному входу второго счетчика, при этом, вход устройства дифференцировани соеди5 нен с установочным входом первого счетчика.0 another input is connected to the output of the buffer device, and the output is connected to the installation input of the second counter, while the input of the differentiation device is connected to the installation input of the first counter.

На чертеже приведена структурна электрическа схема предложенно0 го умножител частоты.The drawing shows the structural electrical circuit of the proposed frequency multiplier.

Дискретный умножитель частоты содержит генератор 1 первой опорной частоты, первый счетчик 2, устройство 3 пам ти, устройство 4 сравнени , The discrete frequency multiplier comprises a generator 1 of the first reference frequency, a first counter 2, a device 3 of memory, a device 4 of comparison,

5 генератор 5 второй опорной частоты, второй счетчик 6, буферное устройство 7, элемент ИЛИ 8 и устройство 9 дифференцировани .5, a second reference frequency generator 5, a second counter 6, a buffer device 7, an OR element 8 and a differentiation device 9.

Дискретный умножитель частоты Discrete frequency multiplier

Claims

0 works as follows. When the input potential of the input frequency to be multiplied by the installation input of the first counter 2 is received, the latter is filled with the counting pulses of the first-frequency generator 1. At the end of the resolving potential, the received code is overwritten into the 3-device device. Simultaneously with the formation of the permit potential potential, a short pulse is generated by the differentiation device 9, which is supplied through the OR element 8 to the installation input of the second counter 6. At the end of the zeroing pulse, the second counter 6 begins to fill with counting pulses from the generator 5 of the second reference frequency different from the first reference frequency N times. The resulting code is continuously fed to one input of the 4 device. The second input of the comparator device 4 continuously receives the code from the memory device 3. In case of equality of codes, the comparison device 4 generates a pulse arriving through the buffer device 7 at the input of the element OR 8 and, from its output, at the installation input of the second counter b. The duration of zeroing is determined by the propagation time of the signal from the output of the second counter b to its installation input. After that, the second counter 6 starts again; fill the counting pulses from the generator 5 of the second reference frequency to the formation of the corresponding code. In this case, an output phase phase is formed due to the discreteness of measuring the period of the input frequency to be multiplied. After forming the Nth output signal pulse (when multiplying the input frequency by N), in the second counter 6, a code is generated corresponding to the phase shift of the output signal over a period input frequency. When forming the next period 4 of the input signal, the second counter 6 is set to zero along the circuit of differentiation device 9 - element OR 8, which ensures the synchronization of the output signal and limiting the phase shift. Then the cycle repeats. The positive effect of the proposed discrete frequency multiplier is that it provides an increase in conversion accuracy with respect to the frequency of the output signal, averaged over a certain period of time, as well as achieving synchronism between the input and output frequencies, and the material costs for achieving these properties are negligible. DETAILED DESCRIPTION OF THE INVENTION A discrete frequency multiplier comprising a first reference frequency generator, a first counter, a memory device, a comparison device and a buffer device, as well as a second reference frequency generator and a second counter, the output of which is connected to another input of the comparison device and the the input of the first counter is connected to the installation input of the memory device, which is characterized by the fact that, in order to increase the multiplication accuracy by providing synchronization yhodnogo signal input, administered sequentially-connected differentiating device and an OR gate, the other input of which is connected to the output buffer Nogo device, and an output connected to the input of the installation of the second counter, wherein the differentiating device input coupled to the input of the first counter mounting. Sources of information taken into account in the examination 1. US patent 3798564. cl. 331-1 A, 03/19/74.