SU662945A1 - Multichannel computing device - Google Patents

Description

channel for a certain time, depending on the time interval between two consecutive readings of the ADC code of one channel and the number of channels.

The processing program for individual commands enters the central processor from a permanent storage device (ROM). Processing includes calculating baseline parameters, detecting a peak, calculating the peak area above the baseline, retention time, total peak area, relative peak area, etc., as well as printing the processing results. Each channel's RAM contains data on chromatographic peaks (ADC codes, baseline parameters, peak areas and retention times, initial analysis data), intermediate results of calculations, final results for printing.

After processing the information on one of the channels, processing on the other channel takes place, and the same processing program is used without changing the instruction.

The disadvantages of the known system are the following:

the total amount of RAM has a certain redundancy: RAM cells for storing intermediate results when calculating are duplicated in each RAM block; the number of cells for storing the areas and peak holding times before final calculations and printing should be chosen based on the maximum possible number of peaks in the channel, although the probability of this is very small; the system speed is determined based on the maximum program length executed during the processing time, although the actual processing time varies widely, depending on the information received and therefore some of the processing time remains unused;

the structural complexity of each block increases due to the need to have separate schemes for issuing, receiving and identifying the block address, receiving and issuing numerical information. In addition, information exchange time increases, or an increase in the exchange speed is required.

The aim of the invention is to save equipment and reduce non-productive time.

The goal is achieved by the fact that, in the system, the RAM drive is made in the form of channel zones and a common zone, the inputs of which are connected to the corresponding outputs of the decoder, and the outputs are connected via a number register to the second address input of the permanent storage device, the second output of which is connected to the second the input of the decoder and the third input

a random access memory, the fourth input of which and the third input of the decoder are connected to the fourth output of the central processor and the output of the channel number register.

Diagram of the device shown in the drawing and includes:

analog-to-digital conversion (ADC) unit 1, random access memory 2 (RAM), read only memory 3 (ROM), central processor 4, input device 5, data output device 6. Unit 1 may include separate ADCs for each channel or one ADC with input channel switching.

Random access memory 2 includes a decoder 7, a drive including channel zones 8, 9, 10, 11, a common zone 12 and an address area of a command 13, a register of the number 14.

The central processor includes the register of the channel number 15, the control device 16, the arithmetic unit 17, and the permanent memory device is the address decoder 18, the command accumulator 19, the command register 20.

During the time interval, according to the same program, without changing the address part of the commands, for each channel, information about the peaks stored in the corresponding channel area of the RAM is processed in turn. Switching channel zones during the transition to the processing of the next channel occurs by logical summation to the address of the binary code number from the register of channel number 15 included in the central processor 4. At that, the address of the number specified in the command is changed to the value where K is the channel number , 2 - the number of cells in each channel zone.

Zone 12 has free access through the decoder 7 regardless of the channel number. So, if there is an address of a number in a command larger than, where N is the number of channels, the logical summation of the code from the channel number register to the number address is prohibited.

Zone 12 contains the common for all channels of the cell of intermediate calculation results, a cell for storing data necessary for calculating the final results and for printing or other recording devices.

The presence of zone 12 allows, with an incomplete use of processing time allocated for one channel, to process the data of zone 12 for another channel, which generally reduces the overhead of time.

The rate of entry of chromatographic data is relatively small and, with a small number of channels served simultaneously, the performance requirements

low Taking into account the reduction of these requirements by reducing the overhead of processing time, the design of the calculator devices is simplified.

The command counter as an independent device is missing. Instead of a command counter, a RAM cell is used to store the command address (area 13).

To change the address of the command in a special cycle, the signal from the control unit 16 of the processor 4 through the decoder 7 to register 14 reads the address of the previous command from area 13. To the read command address through the arithmetic unit 17, one is summed. Then, using the decoder for the address of command 18, the next command is read from the command accumulator 19 of the ROM into the register of command 20. The address of the command is remembered again in area 13 of RAM. Storing the command address in RAM also makes it possible to simplify the control signal transfer scheme using the operation of storing a number in RAM with a special indication of the transmission condition for this purpose.

The register number 14 RAM is simultaneously the address register of the ROM, and the command register 20 of the ROM is the address register for RAM. The operation code from the ROM is fed directly to the control unit.

16processor arithmetic unit

17 of the processor 4, which simplifies the processor circuit and reduces the number of communication buses.

Analog-to-digital conversion unit 1, an input device 5 and an output device 6 are connected directly to the arithmetic unit 17.

Claims (2)

1. “Eine Dbersicht der bestehenden Systeme fiir die Datenerfassung un Chromatographic Sabor. Journal of Chromatographic, 1973 No. 77, No. 1, s. 75-89. 2.A new Computing Integrator for Chromatography. Journal of chromatographic Seiluce December, 1971.