SU656058A1 - First difference computing device - Google Patents

Description

reversible counter and through the element of delay to the second input of the ADC, the output of which is connected to the third input of the reversible counter via a frequency doubler. The second output of the trigger is connected to the second input of the second element I and to the fourth input of the reversible counter. The second trigger input is connected to the output of the OR-NOT element, the inputs of which are connected to the corresponding outputs of the reversing counter.

The drawing shows a block diagram of the device.

It contains a generator of 1 cycles, ADC 2, trigger 3, reversible counter 4, the element OR NOT 5, frequency doubler 6, the delay element 7, the element And 8, 9 and the group of elements And 10,11.

The device works as follows.

With the pulse drive, the start-up starts the generator 1. The signal from the output of the generator 1 sets the counter 4 to the initial state. In this case, a signal appears at the output of the element OR NOT 5, which translates trigger 3 into a single state. The same signal from the output of the generator 1 through the delay element 7 triggers the ADC 2. The signal from the single output of the trigger 3 is fed to the inputs of the AND element 8 and the counter 4. The ADC 2 converts the signal V (t) into a digital code that enters through the frequency doubler 6 at the counting input of the counter 4. In this case, the counter 4 during the time interval works on addition. After time t, the signal from the output of oscillator 1 arrives at the counting input of trigger 3. The trigger changes its state, and the counter during the time tg works for subtraction. Consequently, for two adjacent time intervals t j and t (one clock cycle) of counter 4 in it, a double elementary increment of 2dp is formed due to the doubled input frequency. Through time with the arrival of the signal from the output of the generator 1 to the counting input of the trigger 3, the process of adding and calculating, respectively, for the time tj and (lde 1 1,3,5, ...), is repeated.

A full increment is generated in a time T 2mt, where m is the number of cycles of elementary increments.

Since m K / 2 (where K is the number of time intervals t), T CT

Thus, in the case of (1) 1Г (1} + (where e1J (til and ()) values of the input signals at odd and even conversion times, in counter 4, over time t, we get a full negative increment d

4 1.

If within ti + .i (subtraction) we get 3Ha4eHHeU (t i4, i) U (ti) TO, counter 4 will go to zero.

value. In this case, the OR-NOT 5 element generates a signal that changes the state of the trigger 3 and turns on the addition counter. In the process of Addition, the counter 4 accumulates signals of an elementary positive increment of 2 dp. The process of addition continues until the next signal from the output of the generator 1 to the counting input of the trigger 3 is received. As a result, the trigger transfers the counter to the subtraction. The subtraction process, as before, lasts until the formation of a zero, after which the counter switches to addition. In the future, the process of addition and subtraction, in the counter, is similar

Further, the signal through time T with the output of the generator 1 through the corresponding elements And 8 and the first group of elements And 10 or through And 9 and the second group of elements And And outputs the device outputs a Positive or Negative difference.

The invention can be used in the system of automatic stabilization of the consumption of charge material in metallurgical production, which will simplify the system and increase the reliability of its work.

The economic effect according to preliminary data may be 20 thousand rubles. in year.

Claims (2)

Invention Formula A device for calculating the first difference, containing a trigger, an analog-to-digital converter, the first input of which is the information input of the device, a clock generator, the input of which is the control input of the device, the elements AND, the first and second groups of elements AND, the counter whose outputs are connected With the first inputs of the elements of the first and second groups, the outputs of which are informational outputs of the device, characterized in that, in order to simplify the device, the counter is reversible and the device contains OR OR NOT, frequency doubler and delay element; the first output of the clock generator is connected with the first inputs w of the first and second elements AND, the outputs of which are connected respectively with the second inputs of the elements AND of the first and second groups; the second output of the clock generator is connected to the first input of the trigger, the first output of which is connected to the second input of the first element I and to the first input of the reversible counter; the third output of the clock generator is connected directly to the second input of the reversible counter -k through a delay element to the second input of the analog-digit 6th level converter, the output of which is connected to the third input of the reversible counter via a frequency doubler; the second output of the trigger is connected with the second input of the second element And with the fourth input of the reversible counter; the second input of the trigger is connected to the output of the OR-NOT element, the inputs of which are connected to the corresponding outputs of the reversible counter. Sources of information taken into account in the examination 1.Patent of France No. 290585, QW. G 06 G 7 / 1S, 1.971. 2. Author's testimony zlstvo USSR №475618, cl. G 06 F 7/38, 1975. -in