SU640298A1 - System for checking information input-output arrangement - Google Patents

Description

Responsibly with the second output of the control unit and the input of the indicating unit, the fourth and fifth inputs of the control unit are connected respectively to the outputs of the first and second comparison circuits, the first and second outputs of the on-memory memory are connected respectively to the third input of the second circuit and parity, the third input of which is connected to the third output of the storage unit of the verification program, the outputs of the controlled time counter and the parity checker are connected respectively to the sixth and seventh inlets rows of the control unit.

The drawing shows the proposed device, the block diagram.

It contains a test mode setting unit 1, a control unit 2, a mode simulation unit 3, a test program storage unit 4, a RAM block 5, an interface block 6, a control signal comparison circuit 7, a control information comparison circuit 8, control signals time counter 9, parity check unit 10, fault register 11, display unit 12 and registration unit 13. The device works as follows. Block 4 stores test programs of the device under test, and block 3 contains microprograms corresponding to the commands issued by block 4. Block 5 stores arrays of input and output information, standards, and intermediate results. The circuit compared 8 controls the information from the device under test with the reference one stored in block 5. The circuit compared 7 controls the control signals emitted by the device under test comparing them with the reference received from unit 3. The controlled counter 9 produces time testing the time intervals between the arrival of control signals from the device under test. The start of the time reference and the setting of the duration of the time interval are set by the commands from block 3. The parity information control unit 10 provides, controls the information transfer.

The input / output device under test is connected to interface 6 with an interface associated with registration unit 13. The operator using block 1 sets the data necessary to perform the test: test mode in block 2, the starting address of the program being executed is in block 4, the address of the device under test in block 5. Then the operator with a signal from block 1 starts control block 2, which calls from the block 3, the initial start-up firmware, from which the first instruction of the program being executed is read from block 4.

All subsequent operation of the device is determined by the program recorded in block 4. The operation code for each command is sent through block 2 to block 3 to read the corresponding set of microinstructions.

Micro-neracine of block 3, decoding the operation codes of commands, controls the operation of all blocks of the device. Commands of the verification program prepare information for exchange with the device under test, recording command operands in block 5. After that, the exchange is organized with the help of block 6 to output control information, receive and analyze its reactions, and record information about these reactions in block 5. At the end of the exchange and the comparison, the received and reference information (stored in block 5) is compared using the comparison circuit 8. In the exchange process, the correctness of the control signals being checked by the device is checked with the comparison circuit. 7, which compares the actual signals from block 8 and the reference signals emitted by block 3. The device uses a controlled counter 9 time intervals (9) for detecting errors that interrupt the test, recording cases of the absence of response control signals from the device under test in the course of certain time intervals. All transfers of information are monitored by unit 10 by modulo-2 modulated control information. Detected faults through block 2 are recorded in register 11. For each of the detected non-distortions, the device stops working, and detailed information about the essence and location of the malfunction is displayed for the operator on block 12 indication, as well as through blocks 5 and 6 to block 13 registration. From unit 1, the test mode can be set to the diagnostic mode. In this mode, for each fault, the shutdown is not performed, but the entire program is executed, then in block 13 the numbers of the un-equal blocks of the device under test are printed.

With the help of unit 1, the operator, controlling the visual test process, the results of which are output in unit 12, has the fundamental ability to intervene in the tests, modify its various stages, and create various artificial tests for verification.

Thus, reducing the number of manual operations performed by operations allows for faster testing.

Claims (2)

1. USSR Author's Certificate No. 370609, cl. G 06F 11/04, 1969. 2. USSR author's certificate number 415662, cl. G 06F 11/04, 1972.